linux-kernel - Re: [PATCH v1 2/4] dt-bindings: clock: rk3368: add CLK_I2S_8CH_PRE and CLK_I2S_8CH

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Message-ID: <CAPEOAkSpEzVtUqyUJQbDmbmPOjORnAfuehhvo1qqZgAAeY=ZVA@mail.gmail.com>
Date: Sat, 6 Sep 2025 21:34:25 +0800
From: 李维豪 <cn.liweihao@...il.com>
To: Krzysztof Kozlowski <krzk@...nel.org>
Cc: heiko@...ech.de, robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org, 
	devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, 
	linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org, 
	linux-clk@...r.kernel.org
Subject: Re: [PATCH v1 2/4] dt-bindings: clock: rk3368: add CLK_I2S_8CH_PRE
 and CLK_I2S_8CH_FRAC

Hi,

Krzysztof Kozlowski <krzk@...nel.org> 于2025年9月6日周六 15:21写道：
>
> On 06/09/2025 03:34, 李维豪 wrote:
> > Hi,
> >
> > Krzysztof Kozlowski <krzk@...nel.org> 于2025年9月5日周五 22:13写道：
> >>
> >> On 05/09/2025 15:23, WeiHao Li wrote:
> >>> We need a clock id to assign clock parent when use i2s 8ch as audio
> >>> device, CLK_I2S_8CH_FRAC should be CLK_I2S_8CH_PRE parent so we can get
> >>> frequency we want.
> >>>
> >>> Signed-off-by: WeiHao Li <cn.liweihao@...il.com>
> >>> ---
> >>>  include/dt-bindings/clock/rk3368-cru.h | 3 +++
> >>>  1 file changed, 3 insertions(+)
> >>>
> >>> diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h
> >>> index b951e29069..795e721957 100644
> >>> --- a/include/dt-bindings/clock/rk3368-cru.h
> >>> +++ b/include/dt-bindings/clock/rk3368-cru.h
> >>> @@ -183,6 +183,9 @@
> >>>  #define HCLK_BUS             477
> >>>  #define HCLK_PERI            478
> >>>
> >>> +#define CLK_I2S_8CH_PRE              500
> >>
> >> 479
> >>
> >>> +#define CLK_I2S_8CH_FRAC     501
> >>
> >> 480, no?
> >>
> >
> > Neither of these clocks belong to the previous grouping in terms of
> > type, so I chose to start with a new integer id here.
>
> I don't know what is "previous grouping" here, but IDs are abstract and
> are incremented by 1.

In the current kernel code, the RK3368 clock IDs are categorized by
SCLK, ACLK, PCLK, and HCLK.

However, for the I2S 8CH peripheral, the default MCLK output frequency
depends on I2S_8CH_PRE, which has four possible clock sources:
i2s_8ch_src, i2s_8ch_frac, ext_i2s, and xin12m.

The parent clock of i2s_8ch_frac is i2s_8ch_src, and the frequency of
i2s_8ch_src comes from either the CPLL or GPLL.

Due to the clock topology, CLK_I2S_8CH_PRE and CLK_I2S_8CH_FRAC cannot
be simply categorized as SCLK, ACLK, PCLK, and HCLK mentioned above,
so I choose to start counting from a new ID.

If this way of assigning IDs is not appropriate, I can modify it to
increment based on the previous one.

Besh wishes,
WeiHao