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Message-ID: <CAJKOXPdQ0-Bj6xgx4-5BCJphsPymbHrU4kvKTWH7_LZ0KmstJw@mail.gmail.com>
Date: Thu, 25 Sep 2025 17:15:28 +0900
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Pankaj Patil <pankaj.patil@....qualcomm.com>
Cc: Bjorn Andersson <andersson@...nel.org>, Konrad Dybcio <konradybcio@...nel.org>, 
	Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, Prudhvi Yarlagadda <quic_pyarlaga@...cinc.com>, 
	Qiang Yu <qiang.yu@....qualcomm.com>
Subject: Re: [PATCH 19/24] arm64: dts: qcom: glymur: Add support for PCIe5

On Thu, 25 Sept 2025 at 15:34, Pankaj Patil
<pankaj.patil@....qualcomm.com> wrote:
>
> From: Prudhvi Yarlagadda <quic_pyarlaga@...cinc.com>
>
> Describe PCIe5 controller and PHY. Also add required system resources like
> regulators, clocks, interrupts and registers configuration for PCIe5.
>
> Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@...cinc.com>
> Signed-off-by: Qiang Yu <qiang.yu@....qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@....qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/glymur.dtsi | 208 ++++++++++++++++++++++++++++++++++-
>  1 file changed, 207 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index e6e001485747785fd29c606773cba7793bbd2a5c..17a07d33b9396dba00e61a3b4260fa1a535600f2 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -951,7 +951,7 @@ gcc: clock-controller@...000 {
>                                  <0>,
>                                  <0>,
>                                  <0>,
> -                                <0>;
> +                                <&pcie5_phy>;

No, you just added this line.

Don't add wrong code just to fix it immediately. Qualcomm received
such comment multiple times from me already.

Best regards,
Krzysztof

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