linux-kernel - Re: [PATCH] sound/soc/codecs/wm8978: add missing BCLK divider setup

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Message-ID: <CAN7C2SBsFQJ2qNe0HLfpG+6cuONtpChBnq6fuFkd_CGkLt2c5g@mail.gmail.com>
Date: Tue, 7 Oct 2025 20:48:40 +0800
From: Sune Brian <briansune@...il.com>
To: Charles Keepax <ckeepax@...nsource.cirrus.com>
Cc: Liam Girdwood <lgirdwood@...il.com>, Mark Brown <broonie@...nel.org>, 
	Kuninori Morimoto <kuninori.morimoto.gx@...esas.com>, linux-sound@...r.kernel.org, 
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH] sound/soc/codecs/wm8978: add missing BCLK divider setup

Charles Keepax <ckeepax@...nsource.cirrus.com> 於 2025年10月7日 週二 下午8:11寫道：
>
> On Tue, Oct 07, 2025 at 07:22:10PM +0800, Sune Brian wrote:
> > Charles Keepax <ckeepax@...nsource.cirrus.com> 於 2025年10月7日 週二 下午6:30寫道：
> > > On Fri, Oct 03, 2025 at 05:13:04PM +0800, Brian Sune wrote:
> > > > The original WM8978 codec driver did not set the BCLK (bit clock)
> > > > divider, which can cause audio clocks to be incorrect or unstable
> > > > depending on the sample rate and word length.
> > >
> > > This isn't totally accurate, the driver expects it will be set
> > > through the set_clkdiv callback. Which one could probably argue
> > > is a bit of a more legacy approach, but probably worth calling
> > > that out here.
> >
> > According to actual hardware tests and the WM8978 driver study.
> > There are no bclk register setup in the entire driver. So I am not sure
> > How could this even set through the callback? The IC itself requires
> > 2-wires register load and this can't be done via software level.
>
> /*
>  * Configure WM8978 clock dividers.
>  */
> static int wm8978_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
>                                  int div_id, int div)
> {
>         struct snd_soc_component *component = codec_dai->component;
>         struct wm8978_priv *wm8978 = snd_soc_component_get_drvdata(component);
>         int ret = 0;
>
>         switch (div_id) {
>         case WM8978_OPCLKRATE:
>                 ...
>         case WM8978_BCLKDIV:
>                 if (div & ~0x1c)
>                         return -EINVAL;
>                 snd_soc_component_update_bits(component, WM8978_CLOCKING, 0x1c, div); <<---- HERE
>                 break;
>         default:
>                 return -EINVAL;
>         }
>
>         dev_dbg(component->dev, "%s: ID %d, value %u\n", __func__, div_id, div);
>
>         return ret;
> }
>
> Its not missing its right there. That said your way is probably
> slightly more standard these days, but we should take care of the
> interaction between the two.

What my missing meant is if run with DEBUG flag on that case had never
behave as expected.
MCLK and LRCLK both is correctly outputted. While the current
unpatched version will generate
wrong BCLK complete break the codec. As such I proposed the BCLK patch.
I had not investigate deep why it never calls but the "int div" is
loaded and computed by where is a bit puzzling.
And the loaded it simply with div on actual mclk/2/bit_per_channel is
also incorrect.
As mentioned in previous explanations, the clock register is a fix
table on dividing # that is a LUT with restricted # allowed.

>
> Thanks,
> Charles