linux-kernel - Re: [PATCH v3] ASoC: wm8978: add missing BCLK divider setup

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Message-ID: <CAN7C2SAHy=9S3_DWCEijr09KSc4s516XAcfVbwMhNoFr_PYYrA@mail.gmail.com>
Date: Wed, 8 Oct 2025 22:18:15 +0800
From: Sune Brian <briansune@...il.com>
To: Mark Brown <broonie@...nel.org>
Cc: Charles Keepax <ckeepax@...nsource.cirrus.com>, Liam Girdwood <lgirdwood@...il.com>, 
	Kuninori Morimoto <kuninori.morimoto.gx@...esas.com>, linux-sound@...r.kernel.org, 
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3] ASoC: wm8978: add missing BCLK divider setup

Mark Brown <broonie@...nel.org> 於 2025年10月8日 週三 下午9:40寫道：

> This is not OK, BCLK is 99 which is less than 100 so there are not
> enough BCLK cycles to clock the samples.

What you are questioning won't even fits under normal operation scope
of this codec IC.
This is simply arguing and I really hate these type of conversions.
This is a patch for specific codec IC architecture.
Such automated bclk seeker just runs on expected operatable scope of this codec.
And such patch is to fix missing proper bclk register load from first place.
If there are cases that is this codec is allow but could generate
wrong result on this patch.
Willing to update this patch and learn from my errors.

Any one could do what you are expecting and could runs on this codec.
Happy to learn as much as I can.

Brian