linux-kernel - Re: [PATCH DNM v2 4/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable UFS controller

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Message-ID: <03A4C3DFA86FD6DF+6262361b-e129-4b19-b5eb-42188fa76505@radxa.com>
Date: Thu, 9 Oct 2025 10:16:25 +0800
From: Xilin Wu <sophon@...xa.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
 Bjorn Andersson <andersson@...nel.org>,
 Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, Neil Armstrong <neil.armstrong@...aro.org>,
 Viken Dadhaniya <viken.dadhaniya@....qualcomm.com>,
 Ram Kumar Dwivedi <quic_rdwivedi@...cinc.com>
Subject: Re: [PATCH DNM v2 4/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a:
 Enable UFS controller

On 10/8/2025 5:53 PM, Konrad Dybcio wrote:
> On 9/15/25 9:34 AM, Xilin Wu wrote:
>> On 9/15/2025 3:24 PM, Konrad Dybcio wrote:
>>> On 9/14/25 5:57 PM, Xilin Wu wrote:
>>>> Add and enable UFS related nodes for this board.
>>>>
>>>> Note that UFS Gear-4 Rate-B is unstable due to board and UFS module design
>>>> limitations. UFS on this board is stable when working at Gear-4 Rate-A.
>>>>
>>>> Signed-off-by: Xilin Wu <sophon@...xa.com>
>>>>
>>>> ---
>>>>
>>>> This change depends on the following patch series:
>>>> https://lore.kernel.org/all/20250902164900.21685-1-quic_rdwivedi@quicinc.com/
>>>> ---
>>>>    .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts     | 29 ++++++++++++++++++++++
>>>>    1 file changed, 29 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
>>>> index d30cddfc3eff07237c7e3480a5d42b29091d87d6..3bf85d68c97891db1f1f0b84fb5649803948e06f 100644
>>>> --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
>>>> +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
>>>> @@ -482,6 +482,11 @@ &i2c13 {
>>>>        status = "okay";
>>>>    };
>>>>    +/* It takes a long time in ufshcd_init_crypto when enabled */
>>>
>>> Huh? It only turns on some clocks, writes a couple of mmio registers
>>> and turns the clocks back off, could you investigate a little more?
>>
>> More specifically, it takes a long time in `qcom_scm_ice_invalidate_key`. Considering this platform boots from SPI NOR, while TrustZone doesn't really support SPI NOR storage on this platform, there could be something broken in TZ.
> 
> Hm.. if you change the boot order (if you can on your board..) to start
> with UFS (which would require reflashing of all boot sw onto there), does
> this still manifest?

Unfortunately the board is designed to boot from SPI NOR only. And 
there's no way to change that without replacing some resistors on the board.

Just now I tried a v6.17 based kernel, it now simply triggers a reset 
somewhere when ICE is enabled.


-- 
Best regards,
Xilin Wu <sophon@...xa.com>