linux-kernel - Re: [PATCH v2 15/15] arm64: dts: allwinner: h616: add NAND controller

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Message-ID: <2800174.mvXUDI8C0e@jernej-laptop>
Date: Mon, 13 Oct 2025 17:43:39 +0200
From: Jernej Škrabec <jernej.skrabec@...il.com>
To: Miquel Raynal <miquel.raynal@...tlin.com>,
 Richard Weinberger <richard@....at>, Vignesh Raghavendra <vigneshr@...com>,
 Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>, Chen-Yu Tsai <wens@...e.org>,
 Samuel Holland <samuel@...lland.org>,
 Richard Genoud <richard.genoud@...tlin.com>
Cc: Uwe Kleine-König <u.kleine-koenig@...libre.com>,
 Wentao Liang <vulab@...as.ac.cn>, Johan Hovold <johan@...nel.org>,
 Maxime Ripard <mripard@...nel.org>,
 Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
 linux-mtd@...ts.infradead.org, devicetree@...r.kernel.org,
 linux-arm-kernel@...ts.infradead.org, linux-sunxi@...ts.linux.dev,
 linux-kernel@...r.kernel.org, Richard Genoud <richard.genoud@...tlin.com>
Subject: Re: [PATCH v2 15/15] arm64: dts: allwinner: h616: add NAND controller

Dne ponedeljek, 13. oktober 2025 ob 17:26:45 Srednjeevropski poletni čas je Richard Genoud napisal(a):
> The H616 has a NAND controller quite similar to the A10/A23 ones, but
> with some register differences, more clocks (for ECC and MBUS), more ECC
> strengths, so this requires a new compatible string.
> 
> Add the NAND controller node and pins in the device tree.
> 
> Signed-off-by: Richard Genoud <richard.genoud@...tlin.com>
> ---
>  .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 51 +++++++++++++++++++
>  1 file changed, 51 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
> index ceedae9e399b..bb53c6c63836 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
> @@ -304,6 +304,42 @@ mmc2_pins: mmc2-pins {
>  				bias-pull-up;
>  			};
>  
> +			/omit-if-no-ref/
> +			nand_pins: nand-pins {
> +				pins = "PC0", "PC1", "PC2", "PC5", "PC8", "PC9",
> +				       "PC10", "PC11", "PC12", "PC13", "PC14",
> +				       "PC15", "PC16";
> +				function = "nand0";
> +			};
> +
> +			/omit-if-no-ref/
> +			nand_cs0_pin: nand-cs0-pin {
> +				pins = "PC4";
> +				function = "nand0";
> +				bias-pull-up;
> +			};
> +
> +			/omit-if-no-ref/
> +			nand_cs1_pin: nand-cs1-pin {
> +				pins = "PC3";
> +				function = "nand0";
> +				bias-pull-up;
> +			};
> +
> +			/omit-if-no-ref/
> +			nand_rb0_pin: nand-rb0-pin {
> +				pins = "PC6";
> +				function = "nand0";
> +				bias-pull-up;
> +			};
> +
> +			/omit-if-no-ref/
> +			nand_rb1_pin: nand-rb1-pin {
> +				pins = "PC7";
> +				function = "nand0";
> +				bias-pull-up;
> +			};
> +
>  			/omit-if-no-ref/
>  			spi0_pins: spi0-pins {
>  				pins = "PC0", "PC2", "PC4";
> @@ -377,6 +413,21 @@ iommu: iommu@...0000 {
>  			#iommu-cells = <1>;
>  		};
>  
> +		nfc: nand-controller@...1000 {
> +			compatible = "allwinner,sun50i-h616-nand-controller";
> +			reg = <0x04011000 0x1000>;
> +			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND0>,
> +				<&ccu CLK_NAND1>, <&ccu CLK_MBUS_NAND>;
> +			clock-names = "ahb", "mod", "ecc", "mbus";
> +			resets = <&ccu RST_BUS_NAND>;
> +			reset-names = "ahb";
> +			dmas = <&dma 10>;
> +			dma-names = "rxtx";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};

Sorry, forgot to mention. This should be marked as disabled, as most of
the boards don't have NAND connected.

Best regards,
Jernej

> +
>  		mmc0: mmc@...0000 {
>  			compatible = "allwinner,sun50i-h616-mmc",
>  				     "allwinner,sun50i-a100-mmc";
>