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Message-ID: <176099411059.1819853.2443262969720536579.robh@kernel.org>
Date: Mon, 20 Oct 2025 16:01:51 -0500
From: "Rob Herring (Arm)" <robh@...nel.org>
To: Conor Dooley <conor@...nel.org>
Cc: Valentina.FernandezAlanis@...rochip.com,
	Krzysztof Kozlowski <krzk+dt@...nel.org>, linus.walleij@...aro.org,
	Conor Dooley <conor.dooley@...rochip.com>,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	linux-gpio@...r.kernel.org
Subject: Re: [PATCH v2 3/5] dt-bindings: pinctrl: document polarfire soc
 iomux0 pinmux


On Tue, 14 Oct 2025 15:35:36 +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@...rochip.com>
> 
> On Polarfire SoC, iomux0 is responsible for routing functions to either
> Multiprocessor Subsystem (MSS) IOs or to the FPGA fabric, where they
> can either interface with custom RTL or be routed to the FPGA fabric's
> IOs. Document it.
> 
> Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
> ---
>  .../microchip,mpfs-pinctrl-iomux0.yaml        | 88 +++++++++++++++++++
>  .../microchip,mpfs-mss-top-sysreg.yaml        | 13 ++-
>  2 files changed, 100 insertions(+), 1 deletion(-)
>  create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml
> 

Reviewed-by: Rob Herring (Arm) <robh@...nel.org>


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