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Message-ID: <202511071025.JM5nTGnO-lkp@intel.com>
Date: Fri, 7 Nov 2025 11:28:26 +0800
From: kernel test robot <lkp@...el.com>
To: Manivannan Sadhasivam <manivannan.sadhasivam@....qualcomm.com>,
lpieralisi@...nel.org, kwilczynski@...nel.org, mani@...nel.org,
bhelgaas@...gle.com
Cc: llvm@...ts.linux.dev, oe-kbuild-all@...ts.linux.dev, will@...nel.org,
linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
robh@...nel.org, linux-arm-msm@...r.kernel.org,
zhangsenchuan@...incomputing.com,
Manivannan Sadhasivam <manivannan.sadhasivam@....qualcomm.com>
Subject: Re: [PATCH 3/3] PCI: dwc: Skip PME_Turn_Off and L2/L3 transition if
no device is available
Hi Manivannan,
kernel test robot noticed the following build warnings:
[auto build test WARNING on pci/next]
[also build test WARNING on pci/for-linus linus/master v6.18-rc4 next-20251106]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Manivannan-Sadhasivam/PCI-host-common-Add-an-API-to-check-for-any-device-under-the-Root-Ports/20251106-141822
base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
patch link: https://lore.kernel.org/r/20251106061326.8241-4-manivannan.sadhasivam%40oss.qualcomm.com
patch subject: [PATCH 3/3] PCI: dwc: Skip PME_Turn_Off and L2/L3 transition if no device is available
config: arm-randconfig-001-20251107 (https://download.01.org/0day-ci/archive/20251107/202511071025.JM5nTGnO-lkp@intel.com/config)
compiler: clang version 17.0.6 (https://github.com/llvm/llvm-project 6009708b4367171ccdbf4b5905cb6a803753fe18)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251107/202511071025.JM5nTGnO-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@...el.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202511071025.JM5nTGnO-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/pci/controller/dwc/pcie-designware-host.c:1133:6: warning: variable 'ret' is used uninitialized whenever 'if' condition is true [-Wsometimes-uninitialized]
1133 | if (!pci_root_ports_have_device(pci->pp.bridge->bus))
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/pci/controller/dwc/pcie-designware-host.c:1176:9: note: uninitialized use occurs here
1176 | return ret;
| ^~~
drivers/pci/controller/dwc/pcie-designware-host.c:1133:2: note: remove the 'if' if its condition is always false
1133 | if (!pci_root_ports_have_device(pci->pp.bridge->bus))
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1134 | goto stop_link;
| ~~~~~~~~~~~~~~
drivers/pci/controller/dwc/pcie-designware-host.c:1131:9: note: initialize the variable 'ret' to silence this warning
1131 | int ret;
| ^
| = 0
1 warning generated.
vim +1133 drivers/pci/controller/dwc/pcie-designware-host.c
1126
1127 int dw_pcie_suspend_noirq(struct dw_pcie *pci)
1128 {
1129 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
1130 u32 val;
1131 int ret;
1132
> 1133 if (!pci_root_ports_have_device(pci->pp.bridge->bus))
1134 goto stop_link;
1135
1136 /*
1137 * If L1SS is supported, then do not put the link into L2 as some
1138 * devices such as NVMe expect low resume latency.
1139 */
1140 if (dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKCTL) & PCI_EXP_LNKCTL_ASPM_L1)
1141 return 0;
1142
1143 if (pci->pp.ops->pme_turn_off) {
1144 pci->pp.ops->pme_turn_off(&pci->pp);
1145 } else {
1146 ret = dw_pcie_pme_turn_off(pci);
1147 if (ret)
1148 return ret;
1149 }
1150
1151 ret = read_poll_timeout(dw_pcie_get_ltssm, val,
1152 val == DW_PCIE_LTSSM_L2_IDLE ||
1153 val <= DW_PCIE_LTSSM_DETECT_WAIT,
1154 PCIE_PME_TO_L2_TIMEOUT_US/10,
1155 PCIE_PME_TO_L2_TIMEOUT_US, false, pci);
1156 if (ret) {
1157 /* Only log message when LTSSM isn't in DETECT or POLL */
1158 dev_err(pci->dev, "Timeout waiting for L2 entry! LTSSM: 0x%x\n", val);
1159 return ret;
1160 }
1161
1162 /*
1163 * Per PCIe r6.0, sec 5.3.3.2.1, software should wait at least
1164 * 100ns after L2/L3 Ready before turning off refclock and
1165 * main power. This is harmless when no endpoint is connected.
1166 */
1167 udelay(1);
1168
1169 stop_link:
1170 dw_pcie_stop_link(pci);
1171 if (pci->pp.ops->deinit)
1172 pci->pp.ops->deinit(&pci->pp);
1173
1174 pci->suspended = true;
1175
1176 return ret;
1177 }
1178 EXPORT_SYMBOL_GPL(dw_pcie_suspend_noirq);
1179
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
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