linux-kernel - Re: [PATCH 2/3] dma: arm-dma350: add support for shared interrupt mode

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <9b3bc85f-aa32-46e3-9e95-81490ddacaa0@cixtech.com>
Date: Mon, 17 Nov 2025 19:57:46 +0800
From: Jun Guo <jun.guo@...tech.com>
To: Robin Murphy <robin.murphy@....com>, peter.chen@...tech.com,
 fugang.duan@...tech.com, robh@...nel.org, krzk+dt@...nel.org,
 conor+dt@...nel.org, vkoul@...nel.org, ychuang3@...oton.com,
 schung@...oton.com
Cc: dmaengine@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, cix-kernel-upstream@...tech.com,
 linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 2/3] dma: arm-dma350: add support for shared interrupt
 mode


On 11/17/2025 7:32 PM, Robin Murphy wrote:
> On 2025-11-17 1:59 am, Jun Guo wrote:
>> - The arm dma350 controller's hardware implementation varies: some
>>   designs dedicate a separate interrupt line for each channel, while
>>   others have all channels sharing a single interrupt.This patch adds
>>   support for the hardware design where all DMA channels share a
>>   single interrupt.
> 
> We already request the channel interrupts as shared, precisely because
> they could well end up muxed to the same physical interrupt line. I
> missed that the dedicated combined interrupt output had its own separate
> enable, but for that we may as well just set INTREN_ANYCHINTR_EN
> unconditionally - the rest of this seems pointless.
I'm not entirely sure if enabling the INTREN_ANYCHINTR_EN bit to 1 would 
affect the current default scenario where each channel is assigned its 
own interrupt. The hardware design of the chip I'm currently working 
with does not support testing the scenario of individual interrupts per 
channel. If it doesn't cause any issues, I will change it to an 
unconditional configuration.