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Message-ID: <f960540a-e5d5-40e3-a2a5-6a775a17fbee@samsung.com>
Date: Tue, 18 Nov 2025 09:46:09 +0900
From: Youngmin Nam <youngmin.nam@...sung.com>
To: Ivaylo Ivanov <ivo.ivanov.ivanov1@...il.com>, krzk@...nel.org,
s.nawrocki@...sung.com, alim.akhtar@...sung.com, linus.walleij@...aro.org,
peter.griffin@...aro.org, semen.protsenko@...aro.org
Cc: ryu.real@...sung.com, d7271.choe@...sung.com,
linux-arm-kernel@...ts.infradead.org, linux-samsung-soc@...r.kernel.org,
linux-gpio@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [RFT PATCH v2 2/5] pinctrl: samsung: fix incorrect pin-bank
entries on Exynos2200/7885/8890/8895
Hi Ivaylo,
On 11/17/25 22:42, Ivaylo Ivanov wrote:
> On 11/17/25 09:41, Youngmin Nam wrote:
>> This patch corrects wrong pin bank table definitions for 4 SoCs based on
>> their TRMs.
>>
>> Exynos2200
>> - gpq0/1/2 were using EXYNOS_PIN_BANK_EINTN(), which implies a
>> 'bank_type_off' layout (.fld_width = {4,1,2,2,2,2}).
>> - Per the SoC TRM these banks must use the 'alive' layout
>> (.fld_width = {4,1,4,4}).
>> - Switch them to EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, ...).
>>
>> Exynos7885
>> - etc0, etc1: update bank type to match the SoC TRM.
>> - gpq0 is a non-wakeup interrupt bank; change EINTW -> EINTN accordingly.
>>
>> Exynos8890
>> - Per the SoC TRM, rename bank ect0 to gpb3 and mark it as
>> a non-external interrupt bank.
>
> Interesting, so there are disparities between vendor kernel drivers and
> TRM?
>
>> - gpi1, gpi2: update bank type to match the SoC TRM.
>> exynos8895_bank_type_off (.fld_width = {4,1,2,3,2,2}) ->
>> exynos5433_bank_type_off (.fld_width = {4,1,2,4,2,2})
> Vendor kernel [1] points to these being bank_type_4 (4, 1, 2, 3, 2, 2)
>
> [1] https://protect2.fireeye.com/v1/url?k=4f17b83f-2ff52562-4f163370-000babd9f1ba-2f14da64e4262efc&q=1&e=e88c07b3-b735-4e09-975b-82266d6f3d7b&u=https%3A%2F%2Fgithub.com%2Fananjaser1211%2FCronos_8890%2Fblob%2F0460c258d6910628410263dc838a81be8bda6776%2Fdrivers%2Fpinctrl%2Fsamsung%2Fpinctrl-exynos.c%23L1281C24-L1281C35
>
>> - Per the SoC TRM, mark etc1 as a non-external interrupt bank.
>> - apply lower case style for hex numbers.
>>
>> Exynos8895
>> - gpa4 is a non-wakeup interrupt bank per the SoC TRM.
>> change EINTW -> EINTN. (The bank_type itself was correct and is kept
>> unchanged.)
>
> Also differs here [2]
>
> [2] https://protect2.fireeye.com/v1/url?k=5498d3ae-347a4ef3-549958e1-000babd9f1ba-ad745ff8945d06a1&q=1&e=e88c07b3-b735-4e09-975b-82266d6f3d7b&u=https%3A%2F%2Fgithub.com%2FNeternels%2Fexynos8895_kernel%2Fblob%2F5eb1b4159bc466602e7634b1f7a4f471f4c027e2%2Fdrivers%2Fpinctrl%2Fsamsung%2Fpinctrl-exynos.c%23L1799
>
I'm not sure why the vendor driver differs from the TRM,
but since we've identified the mismatch, we should follow the TRM.
>> - apply lower case style for hex numbers.
>>
>> This aligns the pin-bank tables with the documented bitfield layouts and
>> wakeup domains. No DT/ABI change.
>
> I suspect the changes are valid, unless trms also don't contain false
> information. In any case, this makes me wonder if there are more
> instances of such errors for older SoCs.
>
> Reviewed-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@...il.com>
>
Thanks for the review.
I believe the TRM is correct and should be treated as the source of truth.
I checked Exynos 2200, 7870, 7885, 850, 990, 9810, Exynos Auto v9, 8890, and 8895,
and found no issues other than the four SoCs addressed in this patch.
>>
>> Signed-off-by: Youngmin Nam <youngmin.nam@...sung.com>
>> Reviewed-by: Sam Protsenko <semen.protsenko@...aro.org>
>> Tested-by: Sam Protsenko <semen.protsenko@...aro.org>
>
> I wonder, what was this tested on?
Tested on Exynos850(E850-96 board).
>
>> ---
>> .../pinctrl/samsung/pinctrl-exynos-arm64.c | 40 +++++++++----------
>> 1 file changed, 20 insertions(+), 20 deletions(-)
>>
>> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
>> index d11b2d4ca913..b4a7d86b82fe 100644
>> --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
>> +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
>> @@ -95,9 +95,9 @@ static const struct samsung_pin_bank_data exynos2200_pin_banks0[] __initconst =
>> EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x40, "gpa2", 0x08),
>> EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x60, "gpa3", 0x0c),
>> EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x80, "gpa4", 0x10),
>> - EXYNOS_PIN_BANK_EINTN(4, 0xa0, "gpq0"),
>> - EXYNOS_PIN_BANK_EINTN(2, 0xc0, "gpq1"),
>> - EXYNOS_PIN_BANK_EINTN(2, 0xe0, "gpq2"),
>> + EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 4, 0xa0, "gpq0"),
>> + EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 2, 0xc0, "gpq1"),
>> + EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 2, 0xe0, "gpq2"),
>> };
>>
>> /* pin banks of exynos2200 pin-controller - CMGP */
>> @@ -768,12 +768,12 @@ const struct samsung_pinctrl_of_match_data exynos7870_of_data __initconst = {
>>
>> /* pin banks of exynos7885 pin-controller 0 (ALIVE) */
>> static const struct samsung_pin_bank_data exynos7885_pin_banks0[] __initconst = {
>> - EXYNOS_PIN_BANK_EINTN(3, 0x000, "etc0"),
>> - EXYNOS_PIN_BANK_EINTN(3, 0x020, "etc1"),
>> + EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 3, 0x000, "etc0"),
>> + EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 3, 0x020, "etc1"),
>> EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x040, "gpa0", 0x00),
>> EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x060, "gpa1", 0x04),
>> EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x080, "gpa2", 0x08),
>> - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 5, 0x0a0, "gpq0", 0x0c),
>> + EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 5, 0x0a0, "gpq0"),
>> };
>>
>> /* pin banks of exynos7885 pin-controller 1 (DISPAUD) */
>> @@ -1502,7 +1502,7 @@ static const struct samsung_pin_bank_data exynos8890_pin_banks1[] __initconst =
>> /* pin banks of exynos8890 pin-controller 2 (CCORE) */
>> static const struct samsung_pin_bank_data exynos8890_pin_banks2[] __initconst = {
>> /* Must start with EINTG banks, ordered by EINT group number. */
>> - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x000, "etc0", 0x00),
>> + EXYNOS9_PIN_BANK_EINTN(exynos8895_bank_type_off, 2, 0x000, "gpb3"),
>> };
>>
>> /* pin banks of exynos8890 pin-controller 3 (ESE) */
>> @@ -1520,8 +1520,8 @@ static const struct samsung_pin_bank_data exynos8890_pin_banks4[] __initconst =
>> /* pin banks of exynos8890 pin-controller 5 (FSYS0) */
>> static const struct samsung_pin_bank_data exynos8890_pin_banks5[] __initconst = {
>> /* Must start with EINTG banks, ordered by EINT group number. */
>> - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x000, "gpi1", 0x00),
>> - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x020, "gpi2", 0x04),
>> + EXYNOS9_PIN_BANK_EINTG(exynos5433_bank_type_off, 4, 0x000, "gpi1", 0x00),
>> + EXYNOS9_PIN_BANK_EINTG(exynos5433_bank_type_off, 8, 0x020, "gpi2", 0x04),
>> };
>>
>> /* pin banks of exynos8890 pin-controller 6 (FSYS1) */
>> @@ -1544,15 +1544,15 @@ static const struct samsung_pin_bank_data exynos8890_pin_banks8[] __initconst =
>> EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 6, 0x040, "gpd1", 0x08),
>> EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x060, "gpd2", 0x0c),
>> EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x080, "gpd3", 0x10),
>> - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x0A0, "gpb1", 0x14),
>> - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x0C0, "gpb2", 0x18),
>> - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x0E0, "gpb0", 0x1c),
>> + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x0a0, "gpb1", 0x14),
>> + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x0c0, "gpb2", 0x18),
>> + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x0e0, "gpb0", 0x1c),
>> EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 5, 0x100, "gpc0", 0x20),
>> EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 5, 0x120, "gpc1", 0x24),
>> EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 6, 0x140, "gpc2", 0x28),
>> EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x160, "gpc3", 0x2c),
>> EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x180, "gpk0", 0x30),
>> - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 7, 0x1A0, "etc1", 0x34),
>> + EXYNOS9_PIN_BANK_EINTN(exynos8895_bank_type_off, 7, 0x1a0, "etc1"),
>> };
>>
>> /* pin banks of exynos8890 pin-controller 9 (PERIC1) */
>> @@ -1563,9 +1563,9 @@ static const struct samsung_pin_bank_data exynos8890_pin_banks9[] __initconst =
>> EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x040, "gpe6", 0x08),
>> EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x060, "gpj1", 0x0c),
>> EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x080, "gpj2", 0x10),
>> - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x0A0, "gpe2", 0x14),
>> - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x0C0, "gpe3", 0x18),
>> - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x0E0, "gpe4", 0x1c),
>> + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x0a0, "gpe2", 0x14),
>> + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x0c0, "gpe3", 0x18),
>> + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x0e0, "gpe4", 0x1c),
>> EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x100, "gpe1", 0x20),
>> EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x120, "gpe7", 0x24),
>> EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x140, "gpg0", 0x28),
>> @@ -1647,7 +1647,7 @@ static const struct samsung_pin_bank_data exynos8895_pin_banks0[] __initconst =
>> EXYNOS9_PIN_BANK_EINTW(bank_type_alive, 8, 0x040, "gpa1", 0x04),
>> EXYNOS9_PIN_BANK_EINTW(bank_type_alive, 8, 0x060, "gpa2", 0x08),
>> EXYNOS9_PIN_BANK_EINTW(bank_type_alive, 8, 0x080, "gpa3", 0x0c),
>> - EXYNOS9_PIN_BANK_EINTW(bank_type_alive, 7, 0x0a0, "gpa4", 0x24),
>> + EXYNOS9_PIN_BANK_EINTN(bank_type_alive, 7, 0x0a0, "gpa4"),
>> };
>>
>> /* pin banks of exynos8895 pin-controller 1 (ABOX) */
>> @@ -1695,15 +1695,15 @@ static const struct samsung_pin_bank_data exynos8895_pin_banks7[] __initconst =
>> EXYNOS9_PIN_BANK_EINTG(bank_type_off, 3, 0x000, "gpb0", 0x00),
>> EXYNOS9_PIN_BANK_EINTG(bank_type_off, 5, 0x020, "gpc0", 0x04),
>> EXYNOS9_PIN_BANK_EINTG(bank_type_off, 5, 0x040, "gpc1", 0x08),
>> - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x060, "gpc2", 0x0C),
>> + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x060, "gpc2", 0x0c),
>> EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x080, "gpc3", 0x10),
>> EXYNOS9_PIN_BANK_EINTG(bank_type_off, 4, 0x0a0, "gpk0", 0x14),
>> EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x0c0, "gpe5", 0x18),
>> - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x0e0, "gpe6", 0x1C),
>> + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x0e0, "gpe6", 0x1c),
>> EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x100, "gpe2", 0x20),
>> EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x120, "gpe3", 0x24),
>> EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x140, "gpe4", 0x28),
>> - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 4, 0x160, "gpf0", 0x2C),
>> + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 4, 0x160, "gpf0", 0x2c),
>> EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x180, "gpe1", 0x30),
>> EXYNOS9_PIN_BANK_EINTG(bank_type_off, 2, 0x1a0, "gpg0", 0x34),
>> };
>
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