linux-kernel - Re: [PATCH v9 2/3] clk: canaan: Add clock driver for Canaan K230

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Message-ID: <159615d3-cc52-43be-bf6d-5fe717ef1cc4@zohomail.com>
Date: Sun, 21 Dec 2025 23:08:32 +0800
From: Xukai Wang <kingxukai@...omail.com>
To: Jiayu Du <jiayu.riscv@...c.iscas.ac.cn>,
 Michael Turquette <mturquette@...libre.com>, Stephen Boyd
 <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Paul Walmsley <paul.walmsley@...ive.com>,
 Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
 Conor Dooley <conor@...nel.org>
Cc: linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
 Samuel Holland <samuel.holland@...ive.com>,
 Troy Mitchell <TroyMitchell988@...il.com>
Subject: Re: [PATCH v9 2/3] clk: canaan: Add clock driver for Canaan K230


On 2025/12/19 16:02, Jiayu Du wrote:
> On Thu, Nov 27, 2025 at 08:45:13PM +0800, Xukai Wang wrote:
>> This patch provides basic support for the K230 clock, which covers
>> all clocks in K230 SoC.
>>
>> The clock tree of the K230 SoC consists of a 24MHZ external crystal
>> oscillator, PLLs and an external pulse input for timerX, and their
>> derived clocks.
>>
>> Co-developed-by: Troy Mitchell <TroyMitchell988@...il.com>
>> Signed-off-by: Troy Mitchell <TroyMitchell988@...il.com>
>> Signed-off-by: Xukai Wang <kingxukai@...omail.com>
>> ---
>>  drivers/clk/Kconfig    |    6 +
>>  drivers/clk/Makefile   |    1 +
>>  drivers/clk/clk-k230.c | 2443 ++++++++++++++++++++++++++++++++++++++++++++++++
>>  3 files changed, 2450 insertions(+)
> ...
>> diff --git a/drivers/clk/clk-k230.c b/drivers/clk/clk-k230.c
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..8750e9cbac04f30e31d8f2eb395c9b49027ca278
>> --- /dev/null
>> +++ b/drivers/clk/clk-k230.c
>> @@ -0,0 +1,2443 @@
...
> Incorrect register bit setting (bit1) and wrong parent
> clock reference (hs_hclk_high_src_rate) for hs_hclk_src_gate,
> which does not comply with K230 hardware specifications.
> Here is correcting advice:
> Register bit correction: `0x18, 1, 0, 0,` -> `0x18, 0, 0, 0,`
You're right, thanks for the correction. The bit index should be 0, not 1.
> Parent clock correction: `&hs_hclk_high_src_rate.clk.hw` ->
> `&hs_hclk_high_gate.clk.hw`

According to the vendor's code [1], the parent clock of hs_hclk_src is
hs_hclk_high_src.

>
>> +K230_CLK_RATE_FORMAT(hs_hclk_src_rate,
>> +		     K230_HS_HCLK_SRC_RATE,
> ...
>> +K230_CLK_RATE_FORMAT(hs_sd_card_src_rate,
>> +		     K230_HS_SD_CARD_SRC_RATE,
>> +		     1, 1, 0, 0,
>> +		     2, 8, 12, 0x7,
>> +		     0x1C, 31, div, 0x0,
>> +		     false, 0,
>> +		     &pll0_div4.hw);
>> +
> The parent clock of hs_sd_card_src_rate is incorrectly pointed
> to pll0_div4.
> Here is correcting advice:
> `&pll0_div4.hw` → `&hs_sd_card_src_gate.clk.hw`
You're right, that's my mistake. Thanks for pointing it out.
>
>> +K230_CLK_GATE_FORMAT(hs_sd0_card_gate,
>> +		     K230_HS_SD0_CARD_GATE,
>> +		     0x18, 15, 0, 0,
> ...
>> +	},
>> +	.probe = k230_clk_probe,
>> +};
>> +builtin_platform_driver(k230_clk_driver);
>>
>> -- 
>> 2.34.1
>>
Link:

[1]
https://github.com/kendryte/k230_sdk/blob/main/src/little/linux/arch/riscv/boot/dts/kendryte/clock_provider.dtsi#L578