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Message-ID: <CAL_JsqKYsf9dmY3qKx6MVT0-0emTzO=0z32rOzt3070LykhrPA@mail.gmail.com> Date: Fri, 2 Jan 2026 16:34:15 -0600 From: Rob Herring <robh@...nel.org> To: Swamil Jain <s-jain1@...com> Cc: jyri.sarha@....fi, tomi.valkeinen@...asonboard.com, airlied@...il.com, simona@...ll.ch, maarten.lankhorst@...ux.intel.com, mripard@...nel.org, tzimmermann@...e.de, krzk+dt@...nel.org, conor+dt@...nel.org, devarsht@...com, praneeth@...com, bb@...com, vigneshr@...com, dri-devel@...ts.freedesktop.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org Subject: Re: [PATCH] dt-bindings: display: ti,am65x-dss: Add AM62L DSS support On Tue, Dec 30, 2025 at 8:23 AM Swamil Jain <s-jain1@...com> wrote: > > Hi Rob, > > On 12/30/25 07:57, Rob Herring wrote: > > On Wed, Dec 24, 2025 at 07:01:50PM +0530, Swamil Jain wrote: > >> Update the AM65x DSS bindings to support AM62L which has a single video > >> port. Add conditional constraints for AM62L. > >> > >> Signed-off-by: Swamil Jain <s-jain1@...com> > >> --- > >> .../bindings/display/ti/ti,am65x-dss.yaml | 95 +++++++++++++++---- > >> 1 file changed, 76 insertions(+), 19 deletions(-) > >> > >> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml > >> index 38fcee91211e..ce39690df4e5 100644 > >> --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml > >> +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml > >> @@ -36,34 +36,50 @@ properties: > >> reg: > >> description: > >> Addresses to each DSS memory region described in the SoC's TRM. > >> - items: > >> - - description: common DSS register area > >> - - description: VIDL1 light video plane > >> - - description: VID video plane > >> - - description: OVR1 overlay manager for vp1 > >> - - description: OVR2 overlay manager for vp2 > >> - - description: VP1 video port 1 > >> - - description: VP2 video port 2 > >> - - description: common1 DSS register area > >> + oneOf: > >> + - items: > >> + - description: common DSS register area > >> + - description: VIDL1 light video plane > >> + - description: VID video plane > >> + - description: OVR1 overlay manager for vp1 > >> + - description: OVR2 overlay manager for vp2 > >> + - description: VP1 video port 1 > >> + - description: VP2 video port 2 > >> + - description: common1 DSS register area > >> + - items: > >> + - description: common DSS register area > >> + - description: VIDL1 light video plane > >> + - description: OVR1 overlay manager for vp1 > >> + - description: VP1 video port 1 > >> + - description: common1 DSS register area > >> > >> reg-names: > >> - items: > >> - - const: common > >> - - const: vidl1 > >> - - const: vid > >> - - const: ovr1 > >> - - const: ovr2 > >> - - const: vp1 > >> - - const: vp2 > >> - - const: common1 > >> + oneOf: > >> + - items: > >> + - const: common > >> + - const: vidl1 > >> + - const: vid > >> + - const: ovr1 > >> + - const: ovr2 > >> + - const: vp1 > >> + - const: vp2 > >> + - const: common1 > >> + - items: > >> + - const: common > >> + - const: vidl1 > >> + - const: ovr1 > >> + - const: vp1 > >> + - const: common1 > >> > >> clocks: > >> + minItems: 2 > >> items: > >> - description: fck DSS functional clock > >> - description: vp1 Video Port 1 pixel clock > >> - description: vp2 Video Port 2 pixel clock > >> > >> clock-names: > >> + minItems: 2 > >> items: > >> - const: fck > >> - const: vp1 > >> @@ -84,7 +100,8 @@ properties: > >> maxItems: 1 > >> description: phandle to the associated power domain > >> > >> - dma-coherent: true > >> + dma-coherent: > >> + type: boolean > >> > >> ports: > >> $ref: /schemas/graph.yaml#/properties/ports > >> @@ -195,6 +212,46 @@ allOf: > >> port@0: > >> properties: > >> endpoint@1: false > >> + - if: > >> + properties: > >> + compatible: > >> + contains: > >> + const: ti,am62l-dss > >> + then: > >> + properties: > >> + clock-names: > >> + maxItems: 2 > >> + clocks: > >> + maxItems: 2 > >> + reg: > >> + maxItems: 5 > > > > reg-names: > > minItems: 8 > > else: > > properties: > > reg: > > minItems: 8 > > reg-names: > > minItems: 8 > > > > clocks needs similar constraints... > > Sure, will add in v2. > > > > >> + > >> + - if: > >> + properties: > >> + compatible: > >> + contains: > >> + const: ti,am62l-dss > >> + then: > >> + properties: > >> + reg-names: > >> + items: > >> + - const: common > >> + - const: vidl1 > >> + - const: ovr1 > >> + - const: vp1 > >> + - const: common1 > >> + else: > >> + properties: > >> + reg-names: > >> + items: > >> + - const: common > >> + - const: vidl1 > >> + - const: vid > >> + - const: ovr1 > >> + - const: ovr2 > >> + - const: vp1 > >> + - const: vp2 > >> + - const: common1 > > > > Why are you defining the names twice? > > > > For AM62L we don't have "vid", "ovr2" and "vp2", the dtbs_check will fail. > Could you please suggest a better way? You already defined them at the top level. Here in the if/then schema, all you need is 'maxItems: 5' and 'minItems: 8'. But then you already have that as well. Rob
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