linux-kernel - Re: [PATCH v6 03/11] phy: rockchip: samsung-hdptx: Fix coding style alignment

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Message-ID: <bc3d3416-2f7c-4f4a-a90e-2b3d086ff568@linaro.org>
Date: Tue, 13 Jan 2026 09:11:54 +0100
From: Neil Armstrong <neil.armstrong@...aro.org>
To: Cristian Ciocaltea <cristian.ciocaltea@...labora.com>,
 Vinod Koul <vkoul@...nel.org>, Kishon Vijay Abraham I <kishon@...nel.org>,
 Heiko Stuebner <heiko@...ech.de>, Algea Cao <algea.cao@...k-chips.com>,
 Dmitry Baryshkov <lumag@...nel.org>
Cc: kernel@...labora.com, linux-phy@...ts.infradead.org,
 linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 linux-rockchip@...ts.infradead.org
Subject: Re: [PATCH v6 03/11] phy: rockchip: samsung-hdptx: Fix coding style
 alignment

On 1/13/26 00:20, Cristian Ciocaltea wrote:
> Handle a bunch of reported checkpatch.pl complaints:
> 
>    CHECK: Alignment should match open parenthesis
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@...labora.com>
> ---
>   drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 12 ++++++------
>   1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> index 89710066d70c..3f8a7f4f5cd8 100644
> --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> @@ -1624,11 +1624,11 @@ static void rk_hdptx_phy_set_voltage(struct rk_hdptx_phy *hdptx,
>   		regmap_update_bits(hdptx->regmap, LANE_REG(030a) + offset,
>   				   LN_TX_JEQ_EVEN_CTRL_RBR_MASK,
>   				   FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_RBR_MASK,
> -				   ctrl->tx_jeq_even_ctrl));
> +					      ctrl->tx_jeq_even_ctrl));
>   		regmap_update_bits(hdptx->regmap, LANE_REG(030c) + offset,
>   				   LN_TX_JEQ_ODD_CTRL_RBR_MASK,
>   				   FIELD_PREP(LN_TX_JEQ_ODD_CTRL_RBR_MASK,
> -				   ctrl->tx_jeq_odd_ctrl));
> +					      ctrl->tx_jeq_odd_ctrl));
>   		regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset,
>   				   LN_TX_SER_40BIT_EN_RBR_MASK,
>   				   FIELD_PREP(LN_TX_SER_40BIT_EN_RBR_MASK, 0x1));
> @@ -1638,11 +1638,11 @@ static void rk_hdptx_phy_set_voltage(struct rk_hdptx_phy *hdptx,
>   		regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset,
>   				   LN_TX_JEQ_EVEN_CTRL_HBR_MASK,
>   				   FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR_MASK,
> -				   ctrl->tx_jeq_even_ctrl));
> +					      ctrl->tx_jeq_even_ctrl));
>   		regmap_update_bits(hdptx->regmap, LANE_REG(030d) + offset,
>   				   LN_TX_JEQ_ODD_CTRL_HBR_MASK,
>   				   FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR_MASK,
> -				   ctrl->tx_jeq_odd_ctrl));
> +					      ctrl->tx_jeq_odd_ctrl));
>   		regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset,
>   				   LN_TX_SER_40BIT_EN_HBR_MASK,
>   				   FIELD_PREP(LN_TX_SER_40BIT_EN_HBR_MASK, 0x1));
> @@ -1653,11 +1653,11 @@ static void rk_hdptx_phy_set_voltage(struct rk_hdptx_phy *hdptx,
>   		regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset,
>   				   LN_TX_JEQ_EVEN_CTRL_HBR2_MASK,
>   				   FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR2_MASK,
> -				   ctrl->tx_jeq_even_ctrl));
> +					      ctrl->tx_jeq_even_ctrl));
>   		regmap_update_bits(hdptx->regmap, LANE_REG(030d) + offset,
>   				   LN_TX_JEQ_ODD_CTRL_HBR2_MASK,
>   				   FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR2_MASK,
> -				   ctrl->tx_jeq_odd_ctrl));
> +					      ctrl->tx_jeq_odd_ctrl));
>   		regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset,
>   				   LN_TX_SER_40BIT_EN_HBR2_MASK,
>   				   FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2_MASK, 0x1));
> 

Reviewed-by: Neil Armstrong <neil.armstrong@...aro.org>

Thanks,
Neil