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Message-ID: <aec69818-9fd0-4e50-bab9-f5e36304a4a2@lunn.ch>
Date: Wed, 21 Jan 2026 14:15:11 +0100
From: Andrew Lunn <andrew@...n.ch>
To: Chaoyi Chen <kernel@...kyi.com>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Heiko Stuebner <heiko@...ech.de>,
Quentin Schulz <quentin.schulz@...rry.de>,
Jonas Karlman <jonas@...boo.se>,
Chaoyi Chen <chaoyi.chen@...k-chips.com>, Hsun Lai <i@...insx.cn>,
John Clark <inindev@...il.com>, Jimmy Hon <honyuenkwun@...il.com>,
Dragan Simic <dsimic@...jaro.org>,
Michael Riesch <michael.riesch@...labora.com>,
Peter Robinson <pbrobinson@...il.com>,
Alexey Charkov <alchark@...il.com>,
Shawn Lin <shawn.lin@...k-chips.com>,
Sebastian Reichel <sebastian.reichel@...labora.com>,
Andy Yan <andy.yan@...k-chips.com>, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 2/2] arm64: dts: rockchip: Add rk3576 evb2 board
> +&mdio0 {
> + rgmii_phy0: ethernet-phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0x1>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&rgmii_phy0_rst>;
> + reset-assert-us = <20000>;
> + reset-deassert-us = <100000>;
> + reset-gpios = <&gpio3 RK_PD3 GPIO_ACTIVE_LOW>;
> + tx-internal-delay-ps = <1900>;
What PHY is this? Does it actually implement this property?
It is also close to the 2000ps default. Have you put the board in an
environment chamber and run tests at -20C to +70C to see if it will
work with the default 2000ps?
Andrew
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