linux-kernel - Re: [PATCH v10 2/7] qcom-tgu: Add TGU driver

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Message-ID: <64e7cad1-cb7a-45f4-913e-bdceeaa42fc9@oss.qualcomm.com>
Date: Tue, 27 Jan 2026 11:35:28 +0100
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Songwei Chai <songwei.chai@....qualcomm.com>, andersson@...nel.org,
        alexander.shishkin@...ux.intel.com, mike.leach@...aro.org,
        suzuki.poulose@....com, james.clark@....com, krzk+dt@...nel.org,
        conor+dt@...nel.org
Cc: linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-arm-msm@...r.kernel.org, coresight@...ts.linaro.org,
        devicetree@...r.kernel.org, gregkh@...uxfoundation.org
Subject: Re: [PATCH v10 2/7] qcom-tgu: Add TGU driver

On 1/27/26 3:13 AM, Songwei Chai wrote:
> Hi Konrad,
> 
> Sorry for the late reply.
> 
> On 1/13/2026 6:33 PM, Konrad Dybcio wrote:
>> On 1/9/26 3:11 AM, Songwei Chai wrote:
>>> Add driver to support device TGU (Trigger Generation Unit).
>>> TGU is a Data Engine which can be utilized to sense a plurality of
>>> signals and create a trigger into the CTI or generate interrupts to
>>> processors. Add probe/enable/disable functions for tgu.
>>>
>>> Signed-off-by: Songwei Chai <songwei.chai@....qualcomm.com>
>>> ---

[...]

>>> +static inline void TGU_LOCK(void __iomem *addr)
>>> +{
>>> +    do {
>>> +        /* Wait for things to settle */
>>> +        mb();
>>
>> What are we waiting for here?
>>
>>> +        writel_relaxed(0x0, addr + TGU_LAR);
>>
>> If you do a prompt TGU_LOCK()-TGU_UNLOCK() the writes may arrive in
>> the order opposite to what you want, I'd say this shouldn't be _relaxed()
>> and we should probably have a readback here to make sure the effect has
>> taken place immediately
>>
>>> +    } while (0);
>>> +}
>>> +
>>> +static inline void TGU_UNLOCK(void __iomem *addr)
>>> +{
>>> +    do {
>>> +        writel_relaxed(TGU_UNLOCK_OFFSET, addr + TGU_LAR);
>>> +        /* Make sure everyone has seen this */
>>> +        mb();
>>
>> I believe this should be a readback instead
>>
>>> +    } while (0);
>>> +}
> This lock/unlock sequence is intentionally modelled after the existing CoreSight CS_LOCK/CS_UNLOCK helpers, which have been in mainline for a
> long time and are widely used on ARM systems.
> 
> The barriers here are meant to provide CPU-side ordering guarantees
> around the LAR access rather than to wait for the hardware lock/unlock
> to complete. In particular, the intent is to prevent configuration
> accesses from being reordered across the lock/unlock boundary, matching
> the CoreSight programming model.
> 
> I agree that the comments may be misleading in that regard, and I can
> update them to clarify the ordering intent.
> 
> If you still prefer a stricter write + readback sequence here, I’m also
> happy to switch to that for additional conservatism.

If the hardware doesn't mind potentially receiving commands in the
locked state (i.e. they're not dropped), then this seems fine

Otherwise, I think this may end up to random misconfigurations

Konrad