linux-kernel - Re: [PATCH v5 30/31] clk: at91: at91sam9n12: switch to parent_hw and parent

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Message-ID: <7f5838af-b8f0-44ca-ba9d-378a8aeee934@tuxon.dev>
Date: Sat, 31 Jan 2026 16:22:42 +0200
From: Claudiu Beznea <claudiu.beznea@...on.dev>
To: ryan.wanner@...rochip.com, mturquette@...libre.com, sboyd@...nel.org,
 nicolas.ferre@...rochip.com, alexandre.belloni@...tlin.com,
 bmasney@...hat.com, alexander.sverdlin@...il.com,
 varshini.rajendran@...rochip.com
Cc: cristian.birsan@...rochip.com, balamanikandan.gunasundar@...rochip.com,
 linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 linux-kernel@...r.kernel.org
Subject: Re: [PATCH v5 30/31] clk: at91: at91sam9n12: switch to parent_hw and
 parent_data

Same here for the patch title.

On 1/16/26 22:07, ryan.wanner@...rochip.com wrote:
> From: Claudiu Beznea <claudiu.beznea@...on.dev>
> 
> Switch AT91SAM9N12 clocks to use parent_hw and parent_data. Having
> parent_hw instead of parent names improves to clock registration
> speed and re-parenting.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea@...on.dev>
> Signed-off-by: Ryan Wanner <Ryan.Wanner@...rochip.com>
> ---
>   drivers/clk/at91/at91sam9n12.c | 90 +++++++++++++++++++---------------
>   1 file changed, 51 insertions(+), 39 deletions(-)
> 
> diff --git a/drivers/clk/at91/at91sam9n12.c b/drivers/clk/at91/at91sam9n12.c
> index 34dd7645f964..87c28d34f98d 100644
> --- a/drivers/clk/at91/at91sam9n12.c
> +++ b/drivers/clk/at91/at91sam9n12.c
> @@ -51,9 +51,9 @@ static const struct clk_pll_characteristics pllb_characteristics = {
>   	.out = pllb_out,
>   };
>   
> -static const struct {
> +static struct {
>   	char *n;
> -	char *p;
> +	struct clk_hw *parent_hw;
>   	unsigned long flags;
>   	u8 id;
>   } at91sam9n12_systemck[] = {
> @@ -61,12 +61,12 @@ static const struct {
>   	 * ddrck feeds DDR controller and is enabled by bootloader thus we need
>   	 * to keep it enabled in case there is no Linux consumer for it.
>   	 */
> -	{ .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL },
> -	{ .n = "lcdck", .p = "masterck_div", .id = 3 },
> -	{ .n = "uhpck", .p = "usbck",        .id = 6 },
> -	{ .n = "udpck", .p = "usbck",        .id = 7 },
> -	{ .n = "pck0",  .p = "prog0",        .id = 8 },
> -	{ .n = "pck1",  .p = "prog1",        .id = 9 },
> +	{ .n = "ddrck", .id = 2, .flags = CLK_IS_CRITICAL },
> +	{ .n = "lcdck", .id = 3 },
> +	{ .n = "uhpck", .id = 6 },
> +	{ .n = "udpck", .id = 7 },
> +	{ .n = "pck0",  .id = 8 },
> +	{ .n = "pck1",  .id = 9 },
>   };
>   
>   static const struct clk_pcr_layout at91sam9n12_pcr_layout = {
> @@ -111,12 +111,12 @@ static const struct pck at91sam9n12_periphck[] = {
>   
>   static void __init at91sam9n12_pmc_setup(struct device_node *np)
>   {
> +	struct clk_hw *usbck_hw, *hw, *main_rc_hw, *main_osc_hw;
>   	struct clk_range range = CLK_RANGE(0, 0);
>   	const char *slck_name, *mainxtal_name;
> +	struct clk_parent_data parent_data[5];

Same here as in the previous patch, please mention that you've changed the array 
size along with the rationale behind.

The rest LGTM.

Thank you,
Claudiu