Message-ID: <apfr6syofeffm4ffv67viacsi4bvc5hd7ozk3ddcdcl7kisjee@qsbusru4uns2>
Date: Sun, 8 Feb 2026 20:51:33 +0530
From: Manivannan Sadhasivam <manivannan.sadhasivam@....qualcomm.com>
To: Saravana Kannan <saravanak@...nel.org>
Cc: Konrad Dybcio <konrad.dybcio@....qualcomm.com>, robh@...nel.org,
        andersson@...nel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
        qiang.yu@....qualcomm.com
Subject: Re: [PATCH] of: property: Create devlink between PCI Host bridge and
 Root Port suppliers

On Sat, Feb 07, 2026 at 05:27:21PM -0800, Saravana Kannan wrote:
> On Thu, Feb 5, 2026 at 1:01 AM Manivannan Sadhasivam
> <manivannan.sadhasivam@....qualcomm.com> wrote:
> >
> > On Thu, Feb 05, 2026 at 09:50:20AM +0100, Konrad Dybcio wrote:
> > > On 2/5/26 8:06 AM, Manivannan Sadhasivam wrote:
> > > > In the recent times, devicetree started to represent the PCI Host bridge
> > > > supplies like PHY in the Root Port nodes as seen in commit 38fcbfbd4207
> > > > ("dt-bindings: PCI: qcom: Move PHY & reset GPIO to Root Port node"). But
> > > > the Host bridge drivers still need to control these supplies as a part of
> > > > their controller initialization/deinitialization sequence.
> > > >
> > > > So the Host bridge drivers end up parsing the Root Port supplies in their
> > > > probe() and controlled them. A downside to this approach is that the
> > > > devlink dependency between the suppliers and Host bridge is completely
> > > > broken. Due to this, the driver core probes the Host bridge drivers even if
> > > > the suppliers are not ready, causing probe deferrals and setup teardowns in
> > > > probe().
> > > >
> > > > These probe deferrals sometime happen over 1000 times (as reported in Qcom
> > > > Glymur platform) leading to a waste of CPU resources and increase in boot
> > > > time. So to fix these unnecessary deferrals, create devlink between the
> > > > Host bridge and Root Port suppliers in of_fwnode_add_links(). This will
> > > > allow the driver core to probe the Host bridge drivers only when all Root
> > > > Port suppliers are available.
> > > >
> > > > Reported-by: Bjorn Andersson <andersson@...nel.org>
> > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@....qualcomm.com>
> > > > ---
> > >
> 
> 100% NACK to this patch. You are touching a core part of the
> fw_devlink code to fix it for one specific case. This is not the place
> to special case for a property or a framework.
> 
> Please fix it on the PCI framework level please. Couple of options:
> 1. Revert the original patch causing the issue. The patch was from
> Qualcomm and they didn't test it on their own devices?
> 

No, this is not the case. Even though the change is applicable to Qcom, the
design is generic. Let me explain a bit more:

The PCIe Root Complex (aka PCIe controller) IP integrates two components:

1. Host bridge (1 per controller)
2. Root Port (1 or more per controller)

Historically, a single PCIe controller devicetree node represented these two
components as most of the ARM platforms had only one Root Port per controller.
But then we started seeing platforms with multiple Root Ports [1]. So this
created fragmentation w.r.t bindings and controller drivers. So Rob suggested to
move the Root Port specific properties (PHY, PERST#, WAKE#) to Root Port node
even if the platform has a single Root Port per controller. This move aimed at
easing the pain when the IP design moves to multi-Root Port design in the
future. So this is how Qcom moved. Now we mandate all PCIe controller drivers to
split port properties to Root Port node.

But the problem here is, the Root Port properties are not controlled by the Root
Port driver (drivers/pci/pcie/portdrv.c), but by the controller driver itself.
Because, most of the controller drivers need to enable the port properties
before they can program their own CSRs. Since the properties are moved to the
Root Port node, the controller drivers are parsing the properties themselves and
controlling the resources. This works fine from controller driver PoV, but
fwdevlink is broken since the suppliers (PHY...) are now associated with the
Root Port node instead of the controller node. So the fwdevlink cannot associate
suppliers with controller node and allows the driver to probe but only to defer
multiple times. This is not a big concern as of now, but Bjorn started noticing
1000s of such deferrals which increased boot time on Qcom's new Glymur platform.

> 2. PCI does this weird thing of setting the of_node of two different
> devices to the same of_node. Now that you have this new node, I think
> fixing that behavior to use different of_nodes for the two devices
> might be a solution that might work here. I forget the technical terms
> used in the PCI framework, but I think one was a the bus device and
> the other was the root node.
> 

I believe you are referring to controller device (platform) and Root bus device:

mani@...k:~/pci$ ls -l /sys/devices/platform/soc@...c08000.pci/of_node
lrwxrwxrwx 1 root root 0 Feb  8 20:31 /sys/devices/platform/soc@...c08000.pci/of_node -> ../../../../firmware/devicetree/base/soc@...ci@...8000
mani@...k:~/pci$ ls -l /sys/devices/platform/soc@...c08000.pci/pci0004:00/pci_bus/0004:00/of_node
lrwxrwxrwx 1 root root 0 Feb  8 20:41 /sys/devices/platform/soc@...c08000.pci/pci0004:00/pci_bus/0004:00/of_node -> ../../../../../../../firmware/devicetree/base/soc@...ci@...8000

Technically, Root bus origates from the host bridge device and connects to the
Root Port device. So we cannot bind it to Root Port node that we are discussing
here and binding to the controller node would be the correct option.

> 3. Just create device links if you know you have a weird case of
> dependency that fw_devlink doesn't pick up? It's generally more
> painful to get fw_devlink to ignore what it thinks is a dependency,
> but thankfully that's not the case here.
> 

I would love to solve it in the PCI layer itself if there is a way. But I don't
know how. The PCI framework becomes operational only when the controller driver
probes and registers with the framework. But we need to create devlink even
before the controller driver probes.

We do have the PCI class which gets registered during postcore_initcall(), FYI.

> Please continue cc'ing me in future patches trying to address this.
> I'm happy to give guidance if you get stuck.
> 

Sure, thanks for the review. Even I'm not super happy with plumbing PCI
specific code in the core DT layer, but I'm not sure of doing it elsewhere. Any
suggestions from you would be greatly appreciated!

- Mani

-- 
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