netdev - Re: Network card IRQ balancing with Intel 5000 series chipsets

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Message-ID: <7e63f56c0612250454g5520bd6aja0fb9ab2656ff74e@mail.gmail.com>
Date:	Mon, 25 Dec 2006 14:54:45 +0200
From:	"Robert Iakobashvili" <coroberti@...il.com>
To:	"Arjan van de Ven" <arjan@...radead.org>
Cc:	netdev@...r.kernel.org
Subject: Re: Network card IRQ balancing with Intel 5000 series chipsets

Arjan,

On 12/25/06, Arjan van de Ven <arjan@...radead.org> wrote:
> On Mon, 2006-12-25 at 13:26 +0200, Robert Iakobashvili wrote:
> >
> > > Am I understanding you correctly that you want to spread the load of the
> > > networking IRQ roughly equally over 2 cpus (or cores or ..)?
> >
> > Yes, 4 cores.
> >
> > > If so, that is very very suboptimal, especially for networking (since
> > > suddenly a lot of packet processing gets to deal with out of order
> > > receives and cross-cpu reassembly).
> >
> > Agree. Unfortunately, we have a flow of small RTP packets with heavy
> > processing and both Rx and Tx component on a single network card.
> > The application is not too much sensitive to the out of order, etc.
> > Thus, there 3 cores are actually doing nothing, whereas the CPU0
> > is overloaded, preventing system CPU scaling.
>
> in principle the actual work should still be spread over the cores;
> unless you do everything in kernel space that is..

This is the case. The processing is in kernel.

> > Agree, that providing CPU affinity for a network interrupt is a rather
> > reasonable default.
> > However, should a chipset manufacture take from us the very freedom of
> > tuning, freedom of choice?
>
> it can still be done using the TPR (Thread Priority Register) of the
> APIC. It's just... not there in Linux (other OSes do use this).

Interesting.
Have you any specific pointers for doing it (beyond Internet search)?
Your input would be very much appreciated.
Thank you.


-- 
Sincerely,
Robert Iakobashvili,
coroberti %x40 gmail %x2e com
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