netdev - Re: [PATCH 1/1] bnx2x: Tx barriers and locks

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Date:	Tue, 2 Mar 2010 12:38:01 +0100
From:	Stanislaw Gruszka <sgruszka@...hat.com>
To:	Vladislav Zolotarov <vladz@...adcom.com>
Cc:	Michael Chan <mchan@...adcom.com>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	"davem@...emloft.net" <davem@...emloft.net>,
	Eilon Greenstein <eilong@...adcom.com>,
	Matthew Carlson <mcarlson@...adcom.com>
Subject: Re: [PATCH 1/1] bnx2x: Tx barriers and locks

On Tue, Mar 02, 2010 at 02:38:39AM -0800, Vladislav Zolotarov wrote:
> After reading a Pentium Developers Manual I'm afraid I might have assumed wrong and there is needed a read memory barrier to ensure that the bit testing is performed not earlier the specified location in the code flow (due to CPU reordering).

Linux supports more relaxed cpu's than Pentium :)

> Dave, as an author of atomic_ops.txt paper I think u r the best man to ask. Could u pls. clarify that if we need to ensure that the bit testing is needed AFTER the consumer update (namely after the smp_wmb()) I need to replace it with the smp_mb().
> 
> If yes, it's a clear bug and I'll prepare an appropriate patch immediately.

Yes, it's a bug.

Thanks
Stanislaw
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