netdev - Re: [RFC PATCH 0/4] cpsw: support for control module register

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Message-ID: <522D8DB8.5050305@gmail.com>
Date:	Mon, 09 Sep 2013 10:58:32 +0200
From:	Daniel Mack <zonque@...il.com>
To:	Mugunthan V N <mugunthanvnm@...com>
CC:	netdev@...r.kernel.org, davem@...emloft.net, bcousson@...libre.com,
	tony@...mide.com, devicetree-discuss@...ts.ozlabs.org,
	linux-omap@...r.kernel.org
Subject: Re: [RFC PATCH 0/4] cpsw: support for control module register

On 08.09.2013 13:23, Mugunthan V N wrote:
> This patch series adds the support for configuring GMII_SEL register
> of control module to select the phy mode type and also to configure
> the clock source for RMII phy mode whether to use internal clock or
> the external clock from the phy itself.
> 
> Till now CPSW works as this configuration is done in U-Boot and carried
> over to the kernel. But during suspend/resume Control module tends to
> lose its configured value for GMII_SEL register in AM33xx PG1.0, so
> if CPSW is used in RMII or RGMII mode, on resume cpsw is not working
> as GMII_SEL register lost its configuration values.
> 
> The initial version of the patch is done by Daniel Mack but as per
> Tony's comment he wants it as a seperate driver as it is done in USB
> control module. I have created a seperate driver for the same and as
> the merge window is open now and no feature request is accepted I am
> submitting it as RFC for reviews.

Thanks for doing this. It's a somehow expensive approach of writing a
single 32bit register, but I agree it's cleaner to not have this code in
the cpsw driver directly.

For the whole series:

  Tested-by: Daniel Mack <zonque@...il.com>



Daniel

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