netdev - Re: [PATCH 2/2] net: phy: at803x: soft-reset PHY when link goes down

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Message-ID: <528564D8.9050504@cogentembedded.com>
Date:	Fri, 15 Nov 2013 03:03:36 +0300
From:	Sergei Shtylyov <sergei.shtylyov@...entembedded.com>
To:	Daniel Mack <zonque@...il.com>, netdev@...r.kernel.org
CC:	davem@...emloft.net, marek.belisko@...il.com, ujhelyi.m@...il.com
Subject: Re: [PATCH 2/2] net: phy: at803x: soft-reset PHY when link goes down

Hello.

On 11/14/2013 12:07 AM, Daniel Mack wrote:

> When the link goes down and up again quickly and multiple times in a
> row, the AT803x PHY gets stuck and won't recover unless it is soft-reset
> via the BMCR register.

> Unfortunately, there is no way to detect this state, as all registers
> contain perfectly sane values in such cases. Hence, the only option is
> to always soft-reset the PHY when the link goes down.

> Reset logic is based on a patch from Marek Belisko.

> Signed-off-by: Daniel Mack <zonque@...il.com>
> Reported-and-tested-by: Marek Belisko <marek.belisko@...il.com>
> ---
>   drivers/net/phy/at803x.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 52 insertions(+)

> diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
> index bc71947..303c5ae 100644
> --- a/drivers/net/phy/at803x.c
> +++ b/drivers/net/phy/at803x.c
> @@ -32,10 +32,56 @@
>   #define AT803X_DEBUG_SYSTEM_MODE_CTRL		0x05
>   #define AT803X_DEBUG_RGMII_TX_CLK_DLY		BIT(8)
>
> +#define AT803X_BMCR_SOFTRESET			BIT(15)
> +

    This is the standard bit (BMCR_RESET) #define'd in the same file as MII_BMCR.

WBR, Sergei

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