netdev - Re: [PATCH v5] can: add Renesas R-Car CAN driver

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Message-ID: <5310823E.1020104@cogentembedded.com>
Date:	Fri, 28 Feb 2014 16:34:06 +0400
From:	Sergei Shtylyov <sergei.shtylyov@...entembedded.com>
To:	David Laight <David.Laight@...LAB.COM>,
	Marc Kleine-Budde <mkl@...gutronix.de>,
	Geert Uytterhoeven <geert@...ux-m68k.org>
CC:	"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	"wg@...ndegger.com" <wg@...ndegger.com>,
	"linux-can@...r.kernel.org" <linux-can@...r.kernel.org>,
	Linux-sh list <linux-sh@...r.kernel.org>,
	Pavel Kiryukhin <vksavl@...il.com>
Subject: Re: [PATCH v5] can: add Renesas R-Car CAN driver

Hello.

On 28-02-2014 16:17, David Laight wrote:

>>      This is not a 32-bit register but 24- and 8-bit one. I'm afraid we won't
>> be able to test on BE soon as the machine we're debugging on is LE only.
>> Anyway, for the big-endian configured Superhyway bus the big-endian HPB bus
>> the CAN controller resides on shouldn't swap bytes.

> Except that you aren't going to get any cpu I know about to do a bus
> access with only three of the four byte enables asserted (except as part
> of a misaligned 32 bit transfer).

> So you either have four 8-bit registers, or one 32-bit one.

    I have what is described in the manual, 24-bit register allowing 8-, 16-, 
and 32-bit access.

> I'd suggest keeping both parts in the driver data area

    Well, I'm keeping CLKR value in the platform data. But there is absolutely 
no need to keep BCR anywhere because I'd never use the saved value.

> and oring them together before writing to the device.

    That's what I'm doing.

> 	David

WBR, Sergei

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