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Date: Mon, 22 Aug 2016 16:45:00 +0000 From: Yuval Mintz <Yuval.Mintz@...gic.com> To: Raghu Vatsavayi <rvatsavayi@...iumnetworks.com>, David Miller <davem@...emloft.net> CC: netdev <netdev@...r.kernel.org>, Derek Chickles <derek.chickles@...iumnetworks.com>, Satanand Burla <satananda.burla@...iumnetworks.com>, Felix Manlunas <felix.manlunas@...iumnetworks.com>, Raghu Vatsavayi <raghu.vatsavayi@...iumnetworks.com> Subject: RE: [PATCH net-next V3 08/18] liquidio: CN23XX queue manipulation > + while ((READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) > && > + !(READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_QUIET)) > { > + WRITE_ONCE(reg_val, octeon_read_csr64( > + oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no))); > + } Busy-reading registers without any timeout. Couldn't there be corner cases [PCI errors, etc.]? [This is a recurring event in this patch] > +static void cn23xx_disable_io_queues(struct octeon_device *oct) { > + u64 d64 = 0ULL; > + u32 d32 = 0ULL; While true, why bother with the ULLs? > + > + /* Reset the doorbell register for this Input Queue. */ > + octeon_write_csr(oct, CN23XX_SLI_IQ_DOORBELL(q_no), > 0xFFFFFFFF); > + while (((octeon_read_csr64( > + oct, CN23XX_SLI_IQ_DOORBELL(q_no))) != 0ULL) && !, not != 0. > CN23XX_SLI_PKT_IOQ_RING_RST)); > + while (!(READ_ONCE(d64) & (0x1ULL << q_no)) && loop--) { You can use BIT_ULL for this > + /* Reset the doorbell register for this Output Queue. */ > + octeon_write_csr(oct, CN23XX_SLI_OQ_PKTS_CREDIT(q_no), > + 0xFFFFFFFF); > + while (((octeon_read_csr64( > + oct, CN23XX_SLI_OQ_PKTS_CREDIT(q_no))) != 0ULL) !, not != 0.
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