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Date:   Sat, 18 May 2019 22:46:15 +0200
From:   Marek Vasut <>
To:     Andrew Lunn <>
Cc:, Florian Fainelli <>,
        Guenter Roeck <>,
        Heiner Kallweit <>,
        Jean Delvare <>,
Subject: Re: [PATCH V5] net: phy: tja11xx: Add TJA11xx PHY driver

On 5/18/19 10:12 PM, Andrew Lunn wrote:
> On Sat, May 18, 2019 at 06:50:48PM +0200, Marek Vasut wrote:
>> On 5/18/19 4:14 PM, Andrew Lunn wrote:
>>> On Sat, May 18, 2019 at 01:51:23AM +0200, Marek Vasut wrote:
>>>> Add driver for the NXP TJA1100 and TJA1101 PHYs. These PHYs are special
>>>> BroadRReach 100BaseT1 PHYs used in automotive.
>>> Hi Marek
>> Hello Andrew,
>>>> +	}, {
>>>> +		.name		= "NXP TJA1101",
>>>> +		.features       = PHY_BASIC_T1_FEATURES,
>>> One thing i would like to do before this patch goes in is define
>>> ETHTOOL_LINK_MODE_100baseT1_Full_BIT in ethtool.h, and use it here.
>>> We could not do it earlier because were ran out of bits. But with
>>> PHYLIB now using bitmaps, rather than u32, we can.
>>> Once net-next reopens i will submit a patch adding it.
>> I can understand blocking patches from being applied if they have review
>> problems or need to be updated on some existing or even posted feature.
>> But blocking a patch because some future yet-to-be-developed patch is a
>> bit odd.
> Hi Marek
> What i'm trying to avoid is an ABI change. By using
> PHY_BASIC_T1_FEATURES you are saying the device support 100BaseT. It
> does not. It supports 100BaseT1. I want to add 100BaseT1 first, so
> your PHY does not change from 100BaseT to 100BaseT1, which could be
> considered an ABI change.

I would expect PHY_BASIC_T1_FEATURES , with T1 in the middle , would
imply 100baseT1 , but maybe that's a misnomer .

> I'm not suggesting blocking your patch for a long time. I'm already
> 2/3 of the way doing the work. At the latest, i expect to have patches
> submitted in the next few days. And then your driver can go in, using
> this. So by end of next week, your driver can be in.

But someone has to review your patches too, so that would add another
few weeks.

>>> I also see in the data sheet we should be able to correct detect its
>>> features using register 15. So we should extend
>>> genphy_read_abilities().
>> Which bits do you refer to ?
> Register 15, bit 7. This indicates the PHY can do 100BaseT1. I want to
> double check with the 802.3 standard, but i expect this is part of the
> standard.

The PHY does only 100BaseT1 .

Best regards,
Marek Vasut

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