netdev - RE: [PATCH net] gianfar: Don't force RGMII mode after reset, use defaults

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Message-ID: <VI1PR04MB4880787A714A9E49A436AD2496770@VI1PR04MB4880.eurprd04.prod.outlook.com>
Date:   Tue, 12 Nov 2019 17:09:18 +0000
From:   Claudiu Manoil <claudiu.manoil@....com>
To:     "HEMANT RAMDASI (hramdasi)" <hramdasi@...co.com>,
        "Daniel Walker (danielwa)" <danielwa@...co.com>
CC:     "David S . Miller" <davem@...emloft.net>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "Sathish Jarugumalli -X (sjarugum - ARICENT TECHNOLOGIES HOLDINGS
        LIMITED at Cisco)" <sjarugum@...co.com>
Subject: RE: [PATCH net] gianfar: Don't force RGMII mode after reset, use
 defaults

>-----Original Message-----
>From: HEMANT RAMDASI (hramdasi) <hramdasi@...co.com>
>Sent: Tuesday, November 12, 2019 6:56 PM
>To: Daniel Walker (danielwa) <danielwa@...co.com>; Claudiu Manoil
><claudiu.manoil@....com>
>Cc: David S . Miller <davem@...emloft.net>; netdev@...r.kernel.org;
>Sathish Jarugumalli -X (sjarugum - ARICENT TECHNOLOGIES HOLDINGS
>LIMITED at Cisco) <sjarugum@...co.com>
>Subject: Re: [PATCH net] gianfar: Don't force RGMII mode after reset, use
>defaults
>
>    > Reported-by: Daniel Walker <danielwa@...co.com>
>    > Signed-off-by: Claudiu Manoil <claudiu.manoil@....com>
>    > ---
>    >  drivers/net/ethernet/freescale/gianfar.c | 3 ++-
>    >  drivers/net/ethernet/freescale/gianfar.h | 2 +-
>    >  2 files changed, 3 insertions(+), 2 deletions(-)
>    >
>    > diff --git a/drivers/net/ethernet/freescale/gianfar.c
>b/drivers/net/ethernet/freescale/gianfar.c
>    > index 51ad864..0f4d13d 100644
>    > --- a/drivers/net/ethernet/freescale/gianfar.c
>    > +++ b/drivers/net/ethernet/freescale/gianfar.c
>    > @@ -3173,7 +3173,8 @@ void gfar_mac_reset(struct gfar_private *priv)
>    >  	gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
>    >
>    >  	/* Initialize MACCFG2. */
>    > -	tempval = MACCFG2_INIT_SETTINGS;
>    > +	tempval = gfar_read(&regs->maccfg2);
>    > +	tempval |= MACCFG2_PAD_CRC;
>
>This is not in sync with PAD/CRC definition of maccfg2 mentioned in p202 rm.
>

I don know what you mean.  The definition of this bit is:
" Pad and append CRC . This bit is cleared by default.
This bit must be set when in half-duplex mode (MACCFG2[Full_Duplex] is cleared).
0 Frames presented to the MAC have a valid length and contain a CRC.
1 The MAC pads all transmitted short frames and appends a CRC to every frame regardless of padding
requirement."

So the driver sets this bit to have small frames padded. It always worked this way,
and I retested on P2020RDB and LS1021RDB and works.
Are you saying that padding does not work on your board with the current upstream code?

-Claudiu