netdev - Re: [PATCH net 0/3] net: fsl/fman: address erratum A011043

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Message-Id: <20200123.211733.1373762254655962948.davem@davemloft.net>
Date:   Thu, 23 Jan 2020 21:17:33 +0100 (CET)
From:   David Miller <davem@...emloft.net>
To:     madalin.bucur@....nxp.com
Cc:     netdev@...r.kernel.org, robh+dt@...nel.org, mark.rutland@....com,
        devicetree@...r.kernel.org
Subject: Re: [PATCH net 0/3] net: fsl/fman: address erratum A011043

From: Madalin Bucur <madalin.bucur@....nxp.com>
Date: Wed, 22 Jan 2020 15:20:26 +0200

> This addresses a HW erratum on some QorIQ DPAA devices.
> 
> MDIO reads to internal PCS registers may result in having
> the MDIO_CFG[MDIO_RD_ER] bit set, even when there is no
> error and read data (MDIO_DATA[MDIO_DATA]) is correct.
> Software may get false read error when reading internal
> PCS registers through MDIO. As a workaround, all internal
> MDIO accesses should ignore the MDIO_CFG[MDIO_RD_ER] bit.
> When the issue was present, one could see such errors
> during boot:
> 
>   mdio_bus ffe4e5000: Error while reading PHY0 reg at 3.3

Series applied.