netdev - Re: [PATCH net-next 1/2] dt-bindings: net: dp83822: Add TI dp83822 phy

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <b79f8df0-add8-4ebb-1784-36cc6c50b285@ti.com>
Date:   Thu, 14 May 2020 15:51:06 -0500
From:   Dan Murphy <dmurphy@...com>
To:     Andrew Lunn <andrew@...n.ch>
CC:     <f.fainelli@...il.com>, <hkallweit1@...il.com>,
        <davem@...emloft.net>, <robh@...nel.org>, <netdev@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
        Rob Herring <robh+dt@...nel.org>
Subject: Re: [PATCH net-next 1/2] dt-bindings: net: dp83822: Add TI dp83822
 phy

Andrew

On 5/14/20 3:50 PM, Andrew Lunn wrote:
>>> Hi Dan
>>>
>>> You say 10/100 Mbps Ethernet PHY, but then list RGMII?
>> Copied from the data sheet.
> O.K. So maybe it can connect over RGMII, but then only run 100Mbps
> over it, rather than 1G.
Yes.  This is not a 1Gbps PHY.  Max is 100Mbps.
>
>> The LED_1 pin can be strapped to be an input to the chip for signal loss
>> detection.  This is an optional feature of the PHY.
>>
>> This property defines the polarity for the 822 LED_1/GPIO input pin.
>>
>> The LOS is not required to be connected to the PHY.  If the preferred method
>> is to use the SFP framework and Processor GPIOs then I can remove this from
>> the patch set.
>>
>> And if a user would like to use the feature then they can add it.
> Well, both options are supported by the hardware. So i'm wondering if
> we need to support both. So one property indicating the LOS is
> actually connected to the PHY and a second indicating the polarity?

Why would we need 2?  The SFP core would need to know that the LOS is 
connected to the PHY.

The PHY is strapped to configure the LED_1 as a GPIO input.  I am not 
seeing a register that we can force this configuration.

Data sheet says

Note: To enable 100Base-FX Signal Detection on LED_1 (pin #24), strap 
SD_EN = '1'

So we can read the straps to see if the PHY is connected as the LOS 
input and set the polarity.  But if we are in fiber mode and that pin is 
not strapped for LOS then this setting takes no affect on the PHY.  So 
even reading the straps just allows us to bypass the polarity write.

Dan

>
> 	 Andrew