Message-ID: <20210419214910.hbwry2cnjn6d7crf@skbuf>
Date:   Tue, 20 Apr 2021 00:49:10 +0300
From:   Vladimir Oltean <olteanv@...il.com>
To:     Jakub Kicinski <kuba@...nel.org>
Cc:     "David S. Miller" <davem@...emloft.net>, netdev@...r.kernel.org,
        Po Liu <po.liu@....com>,
        Claudiu Manoil <claudiu.manoil@....com>,
        Alex Marginean <alexandru.marginean@....com>,
        Rob Herring <robh+dt@...nel.org>,
        Shawn Guo <shawnguo@...nel.org>,
        linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
        Russell King - ARM Linux admin <linux@...linux.org.uk>,
        Andrew Lunn <andrew@...n.ch>, Michael Walle <michael@...le.cc>,
        Vladimir Oltean <vladimir.oltean@....com>
Subject: Re: [PATCH net-next 0/5] Flow control for NXP ENETC

Hi Jakub,

On Mon, Apr 19, 2021 at 02:04:42PM -0700, Jakub Kicinski wrote:
> On Sat, 17 Apr 2021 02:42:20 +0300 Vladimir Oltean wrote:
> > From: Vladimir Oltean <vladimir.oltean@....com>
> > 
> > This patch series contains logic for enabling the lossless mode on the
> > RX rings of the ENETC, and the PAUSE thresholds on the internal FIFO
> > memory.
> > 
> > During testing it was found that, with the default FIFO configuration,
> > a sender which isn't persuaded by our PAUSE frames and keeps sending
> > will cause some MAC RX frame errors. To mitigate this, we need to ensure
> > that the FIFO never runs completely full, so we need to fix up a setting
> > that was supposed to be configured well out of reset. Unfortunately this
> > requires the addition of a new mini-driver.
> 
> FWIW back in the day when I was working on more advanced devices than 
> I deal with these days I was expecting to eventually run into this as
> well and create some form of devlink umbrella. IMHO such "mini driver"
> is a natural place for a devlink instance, and not the PFs/ports.
> Is this your thinking as well? AFAICT enetc doesn't implement devlink
> today so you start from whatever model works best without worrying
> about backward compat.

Sorry, but I am not sure if I understood the central idea of what you
were trying to transmit. What is 'a devlink instance and not the PFs'?
I am not aware of how a single devlink instance can be exposed for a
piece of hardware presenting itself as multiple PFs with multiple driver
instances running asynchronously and potentially being assigned to AMP
software execution environments (other cores running non-Linux, and most
probably Linux is not even the privileged execution environment which
has write access to the FIFO parameters).
Are you suggesting that the FIFO size and partitioning characteristics
be exposed through the devlink subsystem? Isn't that what devlink-sb is
for? Also, that would not help with what the IERB driver is trying to
achieve. There isn't anything we want the user to view or fiddle with,
the reality is simply that the FIFO parameters were supposed to be
one-size-fits-all-and-nobody-cares-about-them (the memory usage scheme
of this NIC is smart enough to allow for that, or so I think) but
nonetheless, the hardware defaults need to be touched up. If LS1028A was
a new SoC today we would have probably done this from U-Boot, from the
same logic that already passes the MAC addresses to the PFs through the
IERB, but the ship has kind of sailed for that, bootloaders are stable,
and 'Linux needs this feature' is not a good reason to update them.
So this is all that I would like the IERB driver to do, notice how it's
all writes of predefined values but no reads. For next generation SoCs
with ENETC we'll try our best to not need an IERB driver in Linux at
all. Another option would have been to do these fixups in the arch init
code as a sort of erratum workaround, but I didn't find a place similar
to arch/arm/mach-* for arm64, so I assumed that the arm64 port just
doesn't want to go that route. So here I am with a driver for some
memory writes.

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