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Message-ID: <YNs1F7pgNzDlm/mD@lunn.ch>
Date:   Tue, 29 Jun 2021 16:58:31 +0200
From:   Andrew Lunn <andrew@...n.ch>
To:     Xu Liang <lxu@...linear.com>
Cc:     hkallweit1@...il.com, netdev@...r.kernel.org, davem@...emloft.net,
        kuba@...nel.org, vee.khee.wong@...ux.intel.com,
        linux@...linux.org.uk, hmehrtens@...linear.com,
        tmohren@...linear.com, mohammad.athari.ismail@...el.com
Subject: Re: [PATCH v4 2/2] net: phy: add Maxlinear GPY115/21x/24x driver

> +static int gpy_config_aneg(struct phy_device *phydev)
> +{
> +	bool changed = false;
> +	u32 adv;
> +	int ret;
> +
> +	if (phydev->autoneg == AUTONEG_DISABLE) {
> +		/* Configure half duplex with genphy_setup_forced,
> +		 * because genphy_c45_pma_setup_forced does not support.
> +		 */
> +		return phydev->duplex != DUPLEX_FULL
> +			? genphy_setup_forced(phydev)
> +			: genphy_c45_pma_setup_forced(phydev);
> +	}
> +
> +	ret = genphy_c45_an_config_aneg(phydev);
> +	if (ret < 0)
> +		return ret;
> +	if (ret > 0)
> +		changed = true;
> +
> +	adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
> +	ret = phy_modify_changed(phydev, MII_CTRL1000,
> +				 ADVERTISE_1000FULL | ADVERTISE_1000HALF,
> +				 adv);
> +	if (ret < 0)
> +		return ret;
> +	if (ret > 0)
> +		changed = true;
> +
> +	ret = genphy_c45_check_and_restart_aneg(phydev, changed);
> +	if (ret < 0)
> +		return ret;
> +
> +	if (phydev->interface == PHY_INTERFACE_MODE_USXGMII ||
> +	    phydev->interface == PHY_INTERFACE_MODE_INTERNAL)
> +		return 0;
> +
> +	/* No need to trigger re-ANEG if SGMII link speed is 2.5G
> +	 * or SGMII ANEG is disabled.
> +	 */

Is this correct. Are you using SGMII at 2.5G, or should this comment
be 2500BaseX?

Otherwise, this looks good now.

   Andrew

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