netdev - Re: [PATCH net-next] net: axienet: Allow phytool access to PCS/PMA PHY

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Message-ID: <df768ccb16990f35598d466ad674dfd7b36b8601.camel@calian.com>
Date:   Wed, 30 Jun 2021 18:23:46 +0000
From:   Robert Hancock <robert.hancock@...ian.com>
To:     "linux@...linux.org.uk" <linux@...linux.org.uk>
CC:     "davem@...emloft.net" <davem@...emloft.net>,
        "kuba@...nel.org" <kuba@...nel.org>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "radhey.shyam.pandey@...inx.com" <radhey.shyam.pandey@...inx.com>
Subject: Re: [PATCH net-next] net: axienet: Allow phytool access to PCS/PMA
 PHY

On Wed, 2021-06-30 at 18:46 +0100, Russell King (Oracle) wrote:
> On Wed, Jun 30, 2021 at 11:40:22AM -0600, Robert Hancock wrote:
> > Allow phytool ioctl access to read/write registers in the internal
> > PCS/PMA PHY if it is enabled.
> 
> I wonder if this is something that should happen in phylink?
> 

If there are other drivers which have a PCS which could be accessed with
phytool etc., it might make sense. Right now phylink core doesn't really have
any knowledge that the PCS PHY actually exists as something that can be
accessed via MDIO registers, it just talks to it indirectly through the
mac_config and mac_pcs_get_state callbacks in the driver which then call back
into the c22_pcs helper functions to actually talk to the PCS. 

I'm not sure phylink could generically assume that the PCS can be accessed over
MDIO however, as I believe that the Cadence MACB IP, for example, at least as
implemented in the Xilinx ZynqMP parts, exposes its PCS with some PHY-style
registers but they are just a portion of the device's register space and not
accessed via MDIO, so we'd want to support that kind of setup. I suppose it
could implement an emulated MDIO bus to access those registers for that
purpose?

-- 
Robert Hancock
Senior Hardware Designer, Calian Advanced Technologies
www.calian.com