netdev - Re: [PATCH v1 1/2] driver core: fw_devlink: Add support for FWNODE_FLAG_BROKEN

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Message-ID: <YVXDAQc6RMvDjjFu@lunn.ch>
Date:   Thu, 30 Sep 2021 16:00:33 +0200
From:   Andrew Lunn <andrew@...n.ch>
To:     Vladimir Oltean <olteanv@...il.com>
Cc:     Saravana Kannan <saravanak@...gle.com>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        "Rafael J. Wysocki" <rafael@...nel.org>,
        Linus Walleij <linus.walleij@...aro.org>,
        Vivien Didelot <vivien.didelot@...il.com>,
        Florian Fainelli <f.fainelli@...il.com>,
        "David S. Miller" <davem@...emloft.net>,
        Jakub Kicinski <kuba@...nel.org>, Len Brown <lenb@...nel.org>,
        Alvin Sipraga <ALSI@...g-olufsen.dk>, kernel-team@...roid.com,
        linux-kernel@...r.kernel.org, netdev@...r.kernel.org,
        linux-acpi@...r.kernel.org
Subject: Re: [PATCH v1 1/2] driver core: fw_devlink: Add support for
 FWNODE_FLAG_BROKEN_PARENT

> Andrew is testing with arch/arm/boot/dts/vf610-zii-dev-rev-b.dts.
> 
> Graphically it looks like this:

Nice ASCII art :-)

This shows the flow of Ethernet frames thought the switch
cluster. What is missing, and causing fw_devlink problems is the MDIO
bus master for the PHYs, and the interrupt control where PHY
interrupts are stored, and the linking from the PHY to the interrupt
controller. Physically all these parts are inside the Ethernet switch
package. But Linux models them as separate blocks. This is because in
the general case, they are all discrete blocks. You have a MAC chip,
and a PHY chip, and the PHY interrupt output it connected to a SoC
GPIO.

> 
>  +-----------------------------+
>  |          VF610 SoC          |
>  |          +--------+         |
>  |          |  fec1  |         |
>  +----------+--------+---------+
>                 | DSA master
>                 |
>                 | ethernet = <&fec1>;
>  +--------+----------+---------------------------+
>  |        |  port@6  |                           |
>  |        +----------+                           |
>  |        | CPU port |     dsa,member = <0 0>;   |
>  |        +----------+      -> tree 0, switch 0  |
>  |        |   cpu    |                           |
>  |        +----------+                           |
>  |                                               |
>  |            switch0                            |
>  |                                               |
>  +-----------+-----------+-----------+-----------+

Inside the block above, is the interrupt controller and the MDIO bus
master.


>  |   port@0  |   port@1  |   port@2  |   port@5  |
>  +-----------+-----------+-----------+-----------+
>  |switch0phy0|switch0phy1|switch0phy2|   no PHY  |
>  +-----------+-----------+-----------+-----------+

The control path for these PHYs is over the MDIO bus. They are probed
via the control path bus. These PHYs also have an interrupt output,
which is wired to the interrupt controller above.


>  | user port | user port | user port | DSA port  |
>  +-----------+-----------+-----------+-----------+
>  |    lan0   |    lan1   |    lan2   |    dsa    |
>  +-----------+-----------+-----------+-----------+

   Andrew