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Date: Tue, 5 Oct 2021 07:59:41 +0000 From: Alvin Šipraga <ALSI@...g-olufsen.dk> To: Linus Walleij <linus.walleij@...aro.org> CC: Andrew Lunn <andrew@...n.ch>, Vivien Didelot <vivien.didelot@...il.com>, Florian Fainelli <f.fainelli@...il.com>, Vladimir Oltean <olteanv@...il.com>, "David S . Miller" <davem@...emloft.net>, Jakub Kicinski <kuba@...nel.org>, "netdev@...r.kernel.org" <netdev@...r.kernel.org>, Mauri Sandberg <sandberg@...lfence.com>, DENG Qingfang <dqfext@...il.com> Subject: Re: [PATCH net-next 1/4 v4] net: dsa: rtl8366rb: Support disabling learning Hi Linus, On 10/4/21 10:57 PM, Linus Walleij wrote: > On Thu, Sep 30, 2021 at 12:45 PM Alvin Šipraga <ALSI@...g-olufsen.dk> wrote: > >> Following your discussion with Vladimir [1], did you come to a >> conclusion on how you will handle this? > > I haven't gotten around to running the experiments (short on > time), so I intended to play it safe for now. Unless I feel I have > to. Yeah I understand, it takes some time to figure out how these switches really behave... :-) You have Vladimir's Reviewed-by: tag so I guess this change is OK from the maintainer's perspective. > > BTW: all the patches i have left are extensions to RTL8366RB > specifically so I think it should be fine for you to submit patches > for your switch on top of net-next, maybe we can test this > on you chip too, I suspect it works the same on all Realtek > switches? Generally speaking I don't think that the patches you have sent for 66RB are particularly relevant for the 65MB because the register layout and some chip semantics are totally different. Regarding CPU port learning for the RTL8365MB chip: right now I am playing around with the "third way" Vladimir suggested, by enabling learning selectively only for bridge-layer packets (skb->offload_fwd_mark == true). To begin with I'm not even sure if you have this capability with the RTL8366RB. Alvin > > Yours, > Linus Walleij >
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