netdev - Re: [net-next PATCH 10/13] net: dsa: qca8k: add explicit SGMII PLL enable

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Message-ID: <YV83BAmhHfmDyCjv@lunn.ch>
Date:   Thu, 7 Oct 2021 20:05:56 +0200
From:   Andrew Lunn <andrew@...n.ch>
To:     Ansuel Smith <ansuelsmth@...il.com>
Cc:     Vivien Didelot <vivien.didelot@...il.com>,
        Florian Fainelli <f.fainelli@...il.com>,
        Vladimir Oltean <olteanv@...il.com>,
        "David S. Miller" <davem@...emloft.net>,
        Jakub Kicinski <kuba@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Heiner Kallweit <hkallweit1@...il.com>,
        Russell King <linux@...linux.org.uk>, netdev@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [net-next PATCH 10/13] net: dsa: qca8k: add explicit SGMII PLL
 enable


On Thu, Oct 07, 2021 at 03:35:54PM +0200, Ansuel Smith wrote:
> On Thu, Oct 07, 2021 at 02:29:46AM +0200, Andrew Lunn wrote:
> > On Thu, Oct 07, 2021 at 12:36:00AM +0200, Ansuel Smith wrote:
> > > Support enabling PLL on the SGMII CPU port. Some device require this
> > > special configuration or no traffic is transmitted and the switch
> > > doesn't work at all. A dedicated binding is added to the CPU node
> > > port to apply the correct reg on mac config.
> > 
> > Why not just enable this all the time when the CPU port is in SGMII
> > mode?
> 
> I don't know if you missed the cover letter with the reason. Sgmii PLL
> is a mess. Some device needs it and some doesn't. With a wrong
> configuration the result is not traffic. As it's all messy we decided to
> set the PLL to be enabled with a dedicated binding and set it disabled
> by default. We enouncer more device that require it disabled than device
> that needs it enabled. (in the order of 70 that doesn't needed it and 2
> that requires it enabled or port instability/no traffic/leds problem)

What exactly does this PLL do? Clock recovery of the SGMII clock, and
then using it in the opposite direction? What combinations of PHYs
need it, and which don't?

> > Is it also needed for 1000BaseX?
> > 
> 
> We assume it really depends on the device.

That i find surprising. 1000BaseX and SGMII are very similar. I would
expect a device with requires the PLL enabled for SGMII also needs it
for 1000BaseX.

> > DT properties like this are hard to use. It would be better if the
> > switch can decide for itself if it needs the PLL enabled.
> 
> Again reason in the cover letter sgmii part. Some qca driver have some
> logic based on switch revision. We tried that and it didn't work since
> some device had no traffic with pll enabled (and with the revision set
> to enable pll)

This is my main problem with this patchset. You are adding lots of
poorly documented properties which are proprietary to this switch. And
you are saying, please try all 2^N combinations and see what works
best. That is not very friendly at all.

So it would be good to explain each one in detail. Maybe given the
explanation, we can figure out a way to detect at runtime, and not
need the option. If not, you can add it to the DT binding to help
somebody pick a likely starting point for the 2^N search.

	 Andrew