netdev - Re: mdio: separate gpio-reset property per child phy usecase

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Message-ID: <64248ee1-55dd-b1bd-6c4e-0a272d230e8e@gmail.com>
Date:   Wed, 27 Oct 2021 10:17:46 -0700
From:   Florian Fainelli <f.fainelli@...il.com>
To:     Radhey Shyam Pandey <radheys@...inx.com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        Andrew Lunn <andrew@...n.ch>,
        Heiner Kallweit <hkallweit1@...il.com>,
        Russell King <linux@...linux.org.uk>
Cc:     Michal Simek <michals@...inx.com>,
        Harini Katakam <harinik@...inx.com>
Subject: Re: mdio: separate gpio-reset property per child phy usecase

+PHY library maintainers,

On 10/27/21 5:58 AM, Radhey Shyam Pandey wrote:
> Hi all,
> 
> In a xilinx internal board we have shared GEM MDIO configuration with
> TI DP83867 phy and for proper phy detection both PHYs need prior separate
> GPIO-reset.
> 
> Description:
> There are two GEM ethernet IPs instances GEM0 and GEM1. GEM0 and GEM1 used
> shared MDIO driven by GEM1.
> 
> TI PHYs need prior reset (RESET_B) for PHY detection at defined address. 
> However with current framework limitation " one reset line per PHY present 
> on the MDIO bus" the other PHY get detected at incorrect address and later
> having child PHY node reset property will also not help.
> 
> In order to fix this one possible solution is to allow reset-gpios 
> property to have PHY reset GPIO tuple for each phy. If this
> approach looks fine we can make changes and send out a RFC.

I don't think your proposed solution would work because there is no way
to disambiguate which 'reset-gpios' property applies to which PHY,
unless you use a 'reset-gpio-names' property which encodes the phy
address in there. But even doing so, if the 'reset-gpios' property is
placed within the MDIO controller node then it applies within its scope
which is the MDIO controller. The other reason why it is wrong is
because the MDIO bus itself may need multiple resets to be toggled to be
put in a functional state. This is probably uncommon for MDIO, but it is
not for other types of peripherals with complex asynchronous reset
circuits (the things you love to hate).

The MDIO bus layer supports something like this which is much more
accurate in describing the reset GPIOs pertaining to each PHY device:

	mdio {
		..
		phy0: ethernet-phy@0 {
			reg = <0>;
			reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_HIGH>;
		};
		phy1: ethernet-phy@8 {
			reg = <8>;
			reset-gpios = <&slg7xl45106 6 GPIO_ACTIVE_HIGH>;
		};
	};

The code that will parse that property is in drivers/net/phy/mdio_bus.c
under mdiobus_register_gpiod()/mdiobus_register_reset() and then
mdio_device_reset() called by phy_device_reset() will pulse the per-PHY
device reset line/GPIO.

Are you saying that you tried that and this did not work somehow? Can
you describe in more details how the timing of the reset pulsing affects
the way each TI PHY is going to gets its MDIO address assigned?

Thanks
-- 
Florian