netdev - Re: igc: missing HW timestamps at TX

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Message-ID: <87tu7emqb9.fsf@intel.com>
Date:   Mon, 18 Jul 2022 11:46:34 -0300
From:   Vinicius Costa Gomes <vinicius.gomes@...el.com>
To:     Ferenc Fejes <ferenc.fejes@...csson.com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>
Cc:     "jesse.brandeburg@...el.com" <jesse.brandeburg@...el.com>,
        "anthony.l.nguyen@...el.com" <anthony.l.nguyen@...el.com>
Subject: Re: igc: missing HW timestamps at TX

Hi Ferenc,

Ferenc Fejes <ferenc.fejes@...csson.com> writes:

> (Ctrl+Enter'd by mistake)
>
> My question here: is there anything I can quickly try to avoid that
> behavior? Even when I send only a few (like 10) packets but on fast
> rate (5us between packets) I get missing TX HW timestamps. The receive
> side looks much more roboust, I cannot noticed missing HW timestamps
> there.

There's a limitation in the i225/i226 in the number of "in flight" TX
timestamps they are able to handle. The hardware has 4 sets of registers
to handle timestamps.

There's an aditional issue that the driver as it is right now, only uses
one set of those registers.

I have one only briefly tested series that enables the driver to use the
full set of TX timestamp registers. Another reason that it was not
proposed yet is that I still have to benchmark it and see what is the
performance impact.

If you are feeling adventurous and feel like helping test it, here is
the link:

https://github.com/vcgomes/net-next/tree/igc-multiple-tstamp-timers-lock-new

Cheers,
-- 
Vinicius