netdev - [PATCH 2/2] ARM: imx: imx6sx: Add support for TX clock controls

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Message-Id: <20230711150808.18714-3-vesa.jaaskelainen@vaisala.com>
Date: Tue, 11 Jul 2023 18:08:05 +0300
From: Vesa Jääskeläinen <vesa.jaaskelainen@...sala.com>
To: 
Cc: vesa.jaaskelainen@...sala.com,
	Wei Fang <wei.fang@....com>,
	Shenwei Wang <shenwei.wang@....com>,
	Clark Wang <xiaoning.wang@....com>,
	NXP Linux Team <linux-imx@....com>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>,
	Paolo Abeni <pabeni@...hat.com>,
	Rob Herring <robh+dt@...nel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Russell King <linux@...linux.org.uk>,
	Shawn Guo <shawnguo@...nel.org>,
	Sascha Hauer <s.hauer@...gutronix.de>,
	Pengutronix Kernel Team <kernel@...gutronix.de>,
	Fabio Estevam <festevam@...il.com>,
	netdev@...r.kernel.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org
Subject: [PATCH 2/2] ARM: imx: imx6sx: Add support for TX clock controls

Add device tree configuration support whether Ethernet controller's
ENETx_TX_CLK output driver is enabled.

Also add device tree configuration support whether Ethernet controller's
ENETx_TX_CLK pin is used as reference clock for Ethernet. If not defined
then ref_enetpllx is used as reference clock.

If the new properties are not present then the existing behavior is
preserved.

Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@...sala.com>
---
 arch/arm/mach-imx/mach-imx6sx.c | 27 +++++++++++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/mach-imx6sx.c b/arch/arm/mach-imx/mach-imx6sx.c
index e65ed5218f53..b535579ccaa4 100644
--- a/arch/arm/mach-imx/mach-imx6sx.c
+++ b/arch/arm/mach-imx/mach-imx6sx.c
@@ -17,14 +17,37 @@
 
 static void __init imx6sx_enet_clk_sel(void)
 {
+	struct device_node *enet_np, *from = NULL;
+	unsigned int clock_mux = 0;
+	unsigned int clock_dir = 0;
 	struct regmap *gpr;
+	int i;
+
+	/* Loop thru both FECs found from chip */
+	for (i = 0; i < 2; i++) {
+		enet_np = of_find_compatible_node(from, NULL, "fsl,imx6sx-fec");
+		if (!enet_np)
+			break;
+
+		if (from)
+			of_node_put(from);
+		from = enet_np;
+
+		if (of_property_read_bool(enet_np, "fsl,fec-tx-clock-output"))
+			clock_dir |= 1 << (17 /* ENETx_TX_CLK_DIR */ + i);
+
+		if (of_property_read_bool(enet_np, "fsl,fec-tx-clk-as-ref-clock"))
+			clock_mux |= 1 << (13 /* ENETx_CLK_SEL */ + i);
+	}
+	if (from)
+		of_node_put(from);
 
 	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6sx-iomuxc-gpr");
 	if (!IS_ERR(gpr)) {
 		regmap_update_bits(gpr, IOMUXC_GPR1,
-				   IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK, 0);
+				   IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK, clock_mux);
 		regmap_update_bits(gpr, IOMUXC_GPR1,
-				   IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK, 0);
+				   IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK, clock_dir);
 	} else {
 		pr_err("failed to find fsl,imx6sx-iomux-gpr regmap\n");
 	}
-- 
2.34.1