netdev - RE: [PATCH net] net: phy: marvell10g: fix 88x3310 power up

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Message-ID: <01b701d9ba1c$691d9fa0$3b58dee0$@trustnetic.com>
Date: Wed, 19 Jul 2023 16:38:36 +0800
From: Jiawen Wu <jiawenwu@...stnetic.com>
To: "'Russell King \(Oracle\)'" <linux@...linux.org.uk>
Cc: "'Simon Horman'" <simon.horman@...igine.com>,
	<kabel@...nel.org>,
	<andrew@...n.ch>,
	<hkallweit1@...il.com>,
	<davem@...emloft.net>,
	<edumazet@...gle.com>,
	<kuba@...nel.org>,
	<pabeni@...hat.com>,
	<netdev@...r.kernel.org>
Subject: RE: [PATCH net] net: phy: marvell10g: fix 88x3310 power up

On Wednesday, July 19, 2023 4:27 PM, Russell King (Oracle) wrote:
> On Wed, Jul 19, 2023 at 03:57:30PM +0800, Jiawen Wu wrote:
> > > According to this read though (which is in get_mactype), the write
> > > didn't take effect.
> > >
> > > If you place a delay of 1ms after phy_clear_bits_mmd() in
> > > mv3310_power_up(), does it then work?
> >
> > Yes, I just experimented, it works well.
> 
> Please send a patch adding it, with a comment along the lines of:
> 
> 	/* Sometimes, the power down bit doesn't clear immediately, and
> 	 * a read of this register causes the bit not to clear. Delay
> 	 * 1ms to allow the PHY to come out of power down mode before
> 	 * the next access.
> 	 */

After multiple experiments, I determined that the minimum delay it required
is 55us. Does the delay need to be reduced? But I'm not sure whether it is
related to the system. I use udelay(55) in the test.