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Message-Id: <20230811215322.8679-1-giulio.benetti@benettiengineering.com> Date: Fri, 11 Aug 2023 23:53:22 +0200 From: Giulio Benetti <giulio.benetti@...ettiengineering.com> To: Broadcom internal kernel review list <bcm-kernel-feedback-list@...adcom.com>, Andrew Lunn <andrew@...n.ch>, Heiner Kallweit <hkallweit1@...il.com>, "David S. Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com> Cc: Florian Fainelli <florian.fainelli@...adcom.com>, Russell King <linux@...linux.org.uk>, netdev@...r.kernel.org, linux-kernel@...r.kernel.org, Giulio Benetti <giulio.benetti@...ettiengineering.com>, Jim Reinhart <jimr@...vox.com>, James Autry <jautry@...vox.com>, Matthew Maron <matthewm@...vox.com> Subject: [PATCH] net: phy: broadcom: add support for BCM5221 phy This patch adds the BCM5221 PHY support by reusing brcm_fet_config_intr() and brcm_fet_handle_interrupt() and implementing config_init()/suspend()/resume(). Sponsored by: Tekvox Inc. Cc: Jim Reinhart <jimr@...vox.com> Cc: James Autry <jautry@...vox.com> Cc: Matthew Maron <matthewm@...vox.com> Signed-off-by: Giulio Benetti <giulio.benetti@...ettiengineering.com> --- drivers/net/phy/broadcom.c | 144 +++++++++++++++++++++++++++++++++++++ include/linux/brcmphy.h | 8 +++ 2 files changed, 152 insertions(+) diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c index 59cae0d808aa..99f6c0485f01 100644 --- a/drivers/net/phy/broadcom.c +++ b/drivers/net/phy/broadcom.c @@ -754,6 +754,84 @@ static int brcm_fet_config_init(struct phy_device *phydev) return err; } +static int bcm5221_config_init(struct phy_device *phydev) +{ + int reg, err, err2, brcmtest; + + /* Reset the PHY to bring it to a known state. */ + err = phy_write(phydev, MII_BMCR, BMCR_RESET); + if (err < 0) + return err; + + /* The datasheet indicates the PHY needs up to 1us to complete a reset, + * build some slack here. + */ + usleep_range(1000, 2000); + + /* The PHY requires 65 MDC clock cycles to complete a write operation + * and turnaround the line properly. + * + * We ignore -EIO here as the MDIO controller (e.g.: mdio-bcm-unimac) + * may flag the lack of turn-around as a read failure. This is + * particularly true with this combination since the MDIO controller + * only used 64 MDC cycles. This is not a critical failure in this + * specific case and it has no functional impact otherwise, so we let + * that one go through. If there is a genuine bus error, the next read + * of MII_BRCM_FET_INTREG will error out. + */ + err = phy_read(phydev, MII_BMCR); + if (err < 0 && err != -EIO) + return err; + + reg = phy_read(phydev, MII_BRCM_FET_INTREG); + if (reg < 0) + return reg; + + /* Unmask events we are interested in and mask interrupts globally. */ + reg = MII_BRCM_FET_IR_ENABLE | + MII_BRCM_FET_IR_MASK; + + err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); + if (err < 0) + return err; + + /* Enable auto MDIX */ + err = phy_clear_bits(phydev, BCM5221_AEGSR, BCM5221_AEGSR_MDIX_DIS); + if (err < 0) + return err; + + /* Enable shadow register access */ + brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST); + if (brcmtest < 0) + return brcmtest; + + reg = brcmtest | MII_BRCM_FET_BT_SRE; + + err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg); + if (err < 0) + return err; + + /* Exit low power mode */ + err = phy_clear_bits(phydev, MII_BRCM_FET_SHDW_AUXMODE4, + BCM5221_SHDW_AM4_FORCE_LPM); + if (err < 0) + goto done; + + if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) { + /* Enable auto power down */ + err = phy_set_bits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2, + MII_BRCM_FET_SHDW_AS2_APDE); + } + +done: + /* Disable shadow register access */ + err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest); + if (!err) + err = err2; + + return err; +} + static int brcm_fet_ack_interrupt(struct phy_device *phydev) { int reg; @@ -882,6 +960,61 @@ static int bcm54xx_phy_set_wol(struct phy_device *phydev, return 0; } +static int bcm5221_suspend(struct phy_device *phydev) +{ + int reg, err, err2, brcmtest; + + /* Enable shadow register access */ + brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST); + if (brcmtest < 0) + return brcmtest; + + reg = brcmtest | MII_BRCM_FET_BT_SRE; + + err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg); + if (err < 0) + return err; + + /* Force Low Power Mode with clock enabled */ + err = phy_set_bits(phydev, MII_BRCM_FET_SHDW_AUXMODE4, + BCM5221_SHDW_AM4_EN_CLK_LPM | + BCM5221_SHDW_AM4_FORCE_LPM); + + /* Disable shadow register access */ + err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest); + if (!err) + err = err2; + + return err; +} + +static int bcm5221_resume(struct phy_device *phydev) +{ + int reg, err, err2, brcmtest; + + /* Enable shadow register access */ + brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST); + if (brcmtest < 0) + return brcmtest; + + reg = brcmtest | MII_BRCM_FET_BT_SRE; + + err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg); + if (err < 0) + return err; + + /* Exit Low Power Mode with clock enabled */ + err = phy_clear_bits(phydev, MII_BRCM_FET_SHDW_AUXMODE4, + BCM5221_SHDW_AM4_FORCE_LPM); + + /* Disable shadow register access */ + err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest); + if (!err) + err = err2; + + return err; +} + static int bcm54xx_phy_probe(struct phy_device *phydev) { struct bcm54xx_phy_priv *priv; @@ -1208,6 +1341,16 @@ static struct phy_driver broadcom_drivers[] = { .handle_interrupt = brcm_fet_handle_interrupt, .suspend = brcm_fet_suspend, .resume = brcm_fet_config_init, +}, { + .phy_id = PHY_ID_BCM5221, + .phy_id_mask = 0xfffffff0, + .name = "Broadcom BCM5221", + /* PHY_BASIC_FEATURES */ + .config_init = bcm5221_config_init, + .config_intr = brcm_fet_config_intr, + .handle_interrupt = brcm_fet_handle_interrupt, + .suspend = bcm5221_suspend, + .resume = bcm5221_resume, }, { .phy_id = PHY_ID_BCM5395, .phy_id_mask = 0xfffffff0, @@ -1288,6 +1431,7 @@ static struct mdio_device_id __maybe_unused broadcom_tbl[] = { { PHY_ID_BCM53125, 0xfffffff0 }, { PHY_ID_BCM53128, 0xfffffff0 }, { PHY_ID_BCM89610, 0xfffffff0 }, + { PHY_ID_BCM5221, 0xfffffff0 }, { } }; diff --git a/include/linux/brcmphy.h b/include/linux/brcmphy.h index 5d732f48f787..3d7786cc997d 100644 --- a/include/linux/brcmphy.h +++ b/include/linux/brcmphy.h @@ -12,6 +12,7 @@ #define PHY_ID_BCM50610 0x0143bd60 #define PHY_ID_BCM50610M 0x0143bd70 #define PHY_ID_BCM5241 0x0143bc30 +#define PHY_ID_BCM5221 0x004061e0 #define PHY_ID_BCMAC131 0x0143bc70 #define PHY_ID_BCM5481 0x0143bca0 #define PHY_ID_BCM5395 0x0143bcf0 @@ -330,6 +331,13 @@ #define BCM54XX_WOL_INT_STATUS (MII_BCM54XX_EXP_SEL_WOL + 0x94) +/* BCM5221 Registers */ +#define BCM5221_AEGSR 0x1C +#define BCM5221_AEGSR_MDIX_DIS BIT(11) + +#define BCM5221_SHDW_AM4_EN_CLK_LPM BIT(2) +#define BCM5221_SHDW_AM4_FORCE_LPM BIT(1) + /*****************************************************************************/ /* Fast Ethernet Transceiver definitions. */ /*****************************************************************************/ -- 2.34.1
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