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Message-ID: <ZODUhbw9SDOifv49@vergenet.net>
Date: Sat, 19 Aug 2023 16:41:09 +0200
From: Simon Horman <horms@...nel.org>
To: Daniel Golle <daniel@...rotopia.org>
Cc: Felix Fietkau <nbd@....name>, John Crispin <john@...ozen.org>,
Sean Wang <sean.wang@...iatek.com>,
Mark Lee <Mark-MC.Lee@...iatek.com>,
Lorenzo Bianconi <lorenzo@...nel.org>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org
Subject: Re: [PATCH net] net: ethernet: mtk_eth_soc: add reset bits for MT7988
On Fri, Aug 18, 2023 at 07:15:24PM +0100, Daniel Golle wrote:
> Add bits needed to reset the frame engine on MT7988.
>
> Fixes: 445eb6448ed3 ("net: ethernet: mtk_eth_soc: add basic support for MT7988 SoC")
> Signed-off-by: Daniel Golle <daniel@...rotopia.org>
> ---
> drivers/net/ethernet/mediatek/mtk_eth_soc.c | 76 +++++++++++++++------
> drivers/net/ethernet/mediatek/mtk_eth_soc.h | 11 ++-
> 2 files changed, 64 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
> index fe05c90202699..2482f47313085 100644
> --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
> +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
> @@ -3613,19 +3613,34 @@ static void mtk_hw_reset(struct mtk_eth *eth)
> {
> u32 val;
>
> - if (mtk_is_netsys_v2_or_greater(eth)) {
> + if (mtk_is_netsys_v2_or_greater(eth))
> regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
> +
> + if (mtk_is_netsys_v3_or_greater(eth)) {
> + val = RSTCTRL_PPE0_V3;
> +
> + if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
> + val |= RSTCTRL_PPE1_V3;
> +
> + if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
> + val |= RSTCTRL_PPE2;
> +
> + val |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2;
> + } else if (mtk_is_netsys_v2_or_greater(eth)) {
> val = RSTCTRL_PPE0_V2;
> +
> + if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
> + val |= RSTCTRL_PPE1;
> } else {
> val = RSTCTRL_PPE0;
> }
>
> - if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
> - val |= RSTCTRL_PPE1;
> -
> ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
>
> - if (mtk_is_netsys_v2_or_greater(eth))
> + if (mtk_is_netsys_v3_or_greater(eth))
> + regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
> + 0x6f8ff);
> + else if (mtk_is_netsys_v2_or_greater(eth))
> regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
> 0x3ffffff);
> }
> @@ -3651,13 +3666,21 @@ static void mtk_hw_warm_reset(struct mtk_eth *eth)
> return;
> }
>
> - if (mtk_is_netsys_v2_or_greater(eth))
> + if (mtk_is_netsys_v3_or_greater(eth)) {
> + rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V3;
> + if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
> + rst_mask |= RSTCTRL_PPE1_V3;
> + if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
> + rst_mask |= RSTCTRL_PPE2;
> +
> + rst_mask |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2;
> + } else if (mtk_is_netsys_v2_or_greater(eth)) {
> rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2;
> - else
> + if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
> + rst_mask |= RSTCTRL_PPE1;
> + } else {
> rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0;
> -
> - if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
> - rst_mask |= RSTCTRL_PPE1;
> + }
>
> regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask);
>
Hi Daniel,
The bits set by the code in the above two hunks seem both complex
and similar. At the risk of suggesting excessive complexity,
I do wonder if they can be consolidated somehow.
Maybe the approach you have taken is best as a fix for net.
But a follow-up could be considered for net-next.
Just an idea.
...
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