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Open Source and information security mailing list archives
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Date: Fri, 25 Aug 2023 13:58:48 -0700
From: Stephen Boyd <sboyd@...nel.org>
To: Devi Priya <quic_devipriy@...cinc.com>, agross@...nel.org, andersson@...nel.org, arnd@...db.de, catalin.marinas@....com, conor+dt@...nel.org, devicetree@...r.kernel.org, geert+renesas@...der.be, konrad.dybcio@...aro.org, krzysztof.kozlowski+dt@...aro.org, linux-arm-kernel@...ts.infradead.org, linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org, mturquette@...libre.com, netdev@...r.kernel.org, nfraprado@...labora.com, p.zabel@...gutronix.de, peng.fan@....com, rafal@...ecki.pl, richardcochran@...il.com, robh+dt@...nel.org, will@...nel.org
Cc: quic_devipriy@...cinc.com, quic_saahtoma@...cinc.com
Subject: Re: [PATCH V2 1/7] clk: qcom: clk-alpha-pll: Add NSS HUAYRA ALPHA PLL support for ipq9574
Quoting Devi Priya (2023-08-25 02:12:28)
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index e4ef645f65d1..1c2a72840cd2 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -228,6 +228,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
> [PLL_OFF_ALPHA_VAL] = 0x24,
> [PLL_OFF_ALPHA_VAL_U] = 0x28,
> },
> +
Why the extra newline? All other types aren't this way.
> + [CLK_ALPHA_PLL_TYPE_NSS_HUAYRA] = {
> + [PLL_OFF_L_VAL] = 0x04,
> + [PLL_OFF_ALPHA_VAL] = 0x08,
> + [PLL_OFF_TEST_CTL] = 0x0c,
> + [PLL_OFF_TEST_CTL_U] = 0x10,
> + [PLL_OFF_USER_CTL] = 0x14,
> + [PLL_OFF_CONFIG_CTL] = 0x18,
> + [PLL_OFF_CONFIG_CTL_U] = 0x1c,
> + [PLL_OFF_STATUS] = 0x20,
> + },
> +
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