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Message-ID: <703cae60-5898-e602-f899-06d795b58705@amd.com> Date: Sun, 17 Sep 2023 14:01:05 +0530 From: Raju Rangoju <Raju.Rangoju@....com> To: Tom Lendacky <thomas.lendacky@....com>, Andrew Lunn <andrew@...n.ch> Cc: netdev@...r.kernel.org, davem@...emloft.net, edumazet@...gle.com, kuba@...nel.org, pabeni@...hat.com, Shyam-sundar.S-k@....com Subject: Re: [PATCH net] amd-xgbe: read STAT1 register twice to get correct value On 9/16/2023 12:48 AM, Tom Lendacky wrote: > > > On 9/15/23 07:41, Andrew Lunn wrote: >> On Thu, Sep 14, 2023 at 09:49:44AM +0530, Raju Rangoju wrote: >>> Link status is latched low, so read once to clear >>> and then read again to get current state. >> >> I don't know about your PHY implementation, but within phylib and >> Linux PHY drivers, this is considered wrong. You loose out on being >> notified of the link going down and then back up again. Or up and then >> down again. >> >> But since this is not a Linux PHY driver, you are free to do whatever >> you want... >> >> Also, i believe it is latched, not latched low. So i think your commit >> message is wrong. You should probably check with IEEE 802.3 clause 22. > > Granted I have an old version of IEEE 802.3, but "Table 22-8 - Status > register bit definitions" has: > > 1.2 Link Status 1 = link is up 0 = link is down RO/LL > > So latched low. Thanks, Tom. The following thread (found online) has the detailed info on the IEEE 802.3 Standard that define the Link Status bit: https://microchip.my.site.com/s/article/How-to-correctly-read-the-Ethernet-PHY-Link-Status-bit Thanks, Raju > > Thanks, > Tom > >> >> Andrew >>
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