netdev - Re: [PATCH] net: phy: marvell-88q2xxx: add driver for the Marvell 88Q2220 PHY

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Date: Sat, 16 Dec 2023 17:46:32 +0100
From: Andrew Lunn <andrew@...n.ch>
To: Dimitri Fedrau <dima.fedrau@...il.com>
Cc: Heiner Kallweit <hkallweit1@...il.com>,
	Russell King <linux@...linux.org.uk>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	Stefan Eichenberger <eichest@...il.com>, netdev@...r.kernel.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH] net: phy: marvell-88q2xxx: add driver for the Marvell
 88Q2220 PHY

> +static int mv88q222x_config_aneg_gbit(struct phy_device *phydev)
> +{
> +	int ret;
> +
> +	/* send_s detection threshold, slave and master */
> +	ret = phy_write_mmd(phydev, MDIO_MMD_AN, 0x8032, 0x2020);
> +	if (ret < 0)
> +		return ret;
> +
> +	ret = phy_write_mmd(phydev, MDIO_MMD_AN, 0x8031, 0xa28);
> +	if (ret < 0)
> +		return ret;
> +
> +	ret = phy_write_mmd(phydev, MDIO_MMD_AN, 0x8031, 0xc28);
> +	if (ret < 0)
> +		return ret;

Same register with two different values?

There are a lot of magic values here. Does the datasheet names these
registers? Does it define the bits? Adding #defines would be good.

> +static int mv88q222x_config_aneg_preinit(struct phy_device *phydev)
> +{
> +	int ret, val, i;
> +
> +	/* Enable txdac */
> +	ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8033, 0x6801);
> +	if (ret < 0)
> +		return ret;
> +
> +	/* Disable ANEG */
> +	ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_CTRL, 0x0);
> +	if (ret < 0)
> +		return ret;
> +
> +	/* Set IEEE power down */
> +	ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, 0x840);

0x800 is MDIO_CTRL1_LPOWER. What is the other? It seems like a speed
selection bit?

	  Andrew