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Message-ID: <20240222-rebate-squiggle-d6801d506994@spud>
Date: Thu, 22 Feb 2024 17:57:44 +0000
From: Conor Dooley <conor@...nel.org>
To: Diogo Ivo <diogo.ivo@...mens.com>
Cc: danishanwar@...com, rogerq@...nel.org, davem@...emloft.net,
edumazet@...gle.com, kuba@...nel.org, pabeni@...hat.com,
robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
conor+dt@...nel.org, linux-arm-kernel@...ts.infradead.org,
netdev@...r.kernel.org, devicetree@...r.kernel.org,
jan.kiszka@...mens.com
Subject: Re: [PATCH net-next v3 01/10] dt-bindings: net: Add support for
AM65x SR1.0 in ICSSG
On Wed, Feb 21, 2024 at 03:24:07PM +0000, Diogo Ivo wrote:
> Silicon Revision 1.0 of the AM65x came with a slightly different ICSSG
> support: Only 2 PRUs per slice are available and instead 2 additional
> DMA channels are used for management purposes. We have no restrictions
> on specified PRUs, but the DMA channels need to be adjusted.
>
> Co-developed-by: Jan Kiszka <jan.kiszka@...mens.com>
> Signed-off-by: Jan Kiszka <jan.kiszka@...mens.com>
> Signed-off-by: Diogo Ivo <diogo.ivo@...mens.com>
Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
Cheers,
Conor.
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