netdev - Re: [PATCH v2 net] net: stmmac: dwmac4: extend timeout for VLAN Tag register busy bit check

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Message-ID:
 <PAXPR04MB91856DCDAB12C39631542E33896C2@PAXPR04MB9185.eurprd04.prod.outlook.com>
Date: Fri, 20 Sep 2024 14:24:29 +0000
From: Shenwei Wang <shenwei.wang@....com>
To: Andrew Lunn <andrew@...n.ch>
CC: "David S. Miller" <davem@...emloft.net>, Eric Dumazet
	<edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo Abeni
	<pabeni@...hat.com>, Maxime Coquelin <mcoquelin.stm32@...il.com>,
	"horms@...nel.org" <horms@...nel.org>, Alexandre Torgue
	<alexandre.torgue@...s.st.com>, Jose Abreu <joabreu@...opsys.com>, Ong Boon
 Leong <boon.leong.ong@...el.com>, Wong Vee Khee <vee.khee.wong@...el.com>,
	Chuah Kim Tatt <kim.tatt.chuah@...el.com>, "netdev@...r.kernel.org"
	<netdev@...r.kernel.org>, "linux-stm32@...md-mailman.stormreply.com"
	<linux-stm32@...md-mailman.stormreply.com>,
	"linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>, "imx@...ts.linux.dev"
	<imx@...ts.linux.dev>, dl-linux-imx <linux-imx@....com>
Subject: Re: [PATCH v2 net] net: stmmac: dwmac4: extend timeout for VLAN Tag
 register busy bit check



> -----Original Message-----
> From: Andrew Lunn <andrew@...n.ch>
> Sent: Wednesday, September 18, 2024 6:58 PM
> To: Shenwei Wang <shenwei.wang@....com>
> Cc: David S. Miller <davem@...emloft.net>; Eric Dumazet
> <edumazet@...gle.com>; Jakub Kicinski <kuba@...nel.org>; Paolo Abeni
> <pabeni@...hat.com>; Maxime Coquelin <mcoquelin.stm32@...il.com>;
> horms@...nel.org; Alexandre Torgue <alexandre.torgue@...s.st.com>; Jose
> Abreu <joabreu@...opsys.com>; Ong Boon Leong <boon.leong.ong@...el.com>;
> Wong Vee Khee <vee.khee.wong@...el.com>; Chuah Kim Tatt
> <kim.tatt.chuah@...el.com>; netdev@...r.kernel.org; linux-stm32@...md-
> mailman.stormreply.com; linux-arm-kernel@...ts.infradead.org;
> imx@...ts.linux.dev; dl-linux-imx <linux-imx@....com>
> Subject: [EXT] Re: [PATCH v2 net] net: stmmac: dwmac4: extend timeout for
> VLAN Tag register busy bit check
> > Overnight testing revealed that when EEE is active, the busy bit can
> > remain set for up to approximately 300ms. The new 500ms timeout
> > provides a safety margin.
> 
> Do you know what EEE has to do with VLAN filtering?
> 

The exact design details are not available to me, but my understanding is that the Busy Bit is synchronized to the RX clock 
supplied by the PHY. When EEE is active and the PHY enters LPI state, the RX clock is gated, preventing updates to the Busy Bit.

The question is the significant delay observed, especially considering that the PHY transitions between active and LPI states 
multiple times during this period. There should have a lot of chances to update the Busy Bit sooner when it is in the active state.

> Could there be other registers which suffer from the same problem?
> 

So far I think it only impact the VLAN status register because those bits are driven by another clock instead of CSR clock.
Based on current observations, it appears that this issue primarily affects the VLAN status register. The reason for this 
is that the bits in the VLAN status register are driven by a clock source distinct from the CSR clock.

Regards,
Shenwei

>       Andrew