netdev - Re: [PATCH v2 net] net: stmmac: dwmac4: extend timeout for VLAN Tag register busy bit check

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <e2ca8af5-dfca-4d3e-998c-b90d302ea61b@lunn.ch>
Date: Fri, 20 Sep 2024 20:58:54 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Shenwei Wang <shenwei.wang@....com>
Cc: "David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	Maxime Coquelin <mcoquelin.stm32@...il.com>,
	"horms@...nel.org" <horms@...nel.org>,
	Alexandre Torgue <alexandre.torgue@...s.st.com>,
	Jose Abreu <joabreu@...opsys.com>,
	Ong Boon Leong <boon.leong.ong@...el.com>,
	Wong Vee Khee <vee.khee.wong@...el.com>,
	Chuah Kim Tatt <kim.tatt.chuah@...el.com>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	"linux-stm32@...md-mailman.stormreply.com" <linux-stm32@...md-mailman.stormreply.com>,
	"linux-arm-kernel@...ts.infradead.org" <linux-arm-kernel@...ts.infradead.org>,
	"imx@...ts.linux.dev" <imx@...ts.linux.dev>,
	dl-linux-imx <linux-imx@....com>
Subject: Re: [PATCH v2 net] net: stmmac: dwmac4: extend timeout for VLAN Tag
 register busy bit check

> > Could there be other registers which suffer from the same problem?
> > 
> 
> So far I think it only impact the VLAN status register because those bits are driven by another clock instead of CSR clock.
> Based on current observations, it appears that this issue primarily affects the VLAN status register. The reason for this 
> is that the bits in the VLAN status register are driven by a clock source distinct from the CSR clock.

Thanks for the explanation.

Reviewed-by: Andrew Lunn <andrew@...n.ch>

    Andrew