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Message-ID: <176133844020.2245037.14851736632255812541.stgit@ahduyck-xeon-server.home.arpa> Date: Fri, 24 Oct 2025 13:40:40 -0700 From: Alexander Duyck <alexander.duyck@...il.com> To: netdev@...r.kernel.org Cc: kuba@...nel.org, kernel-team@...a.com, andrew+netdev@...n.ch, hkallweit1@...il.com, linux@...linux.org.uk, pabeni@...hat.com, davem@...emloft.net Subject: [net-next PATCH 1/8] net: phy: Add support for 25, 50 and 100Gbps PMA to genphy_c45_read_pma From: Alexander Duyck <alexanderduyck@...com> Add support for reading 25, 50, and 100G from the PMA interface for a C45 device. By doing this we enable support for future devices that support higher speeds than the current limit of 10G. Signed-off-by: Alexander Duyck <alexanderduyck@...com> --- drivers/net/phy/phy-c45.c | 9 +++++++++ include/uapi/linux/mdio.h | 9 +++++++++ 2 files changed, 18 insertions(+) diff --git a/drivers/net/phy/phy-c45.c b/drivers/net/phy/phy-c45.c index 61670be0f095..2b178a789941 100644 --- a/drivers/net/phy/phy-c45.c +++ b/drivers/net/phy/phy-c45.c @@ -626,6 +626,15 @@ int genphy_c45_read_pma(struct phy_device *phydev) case MDIO_CTRL1_SPEED10G: phydev->speed = SPEED_10000; break; + case MDIO_CTRL1_SPEED25G: + phydev->speed = SPEED_25000; + break; + case MDIO_CTRL1_SPEED50G: + phydev->speed = SPEED_50000; + break; + case MDIO_CTRL1_SPEED100G: + phydev->speed = SPEED_100000; + break; default: phydev->speed = SPEED_UNKNOWN; break; diff --git a/include/uapi/linux/mdio.h b/include/uapi/linux/mdio.h index 6975f182b22c..ff8b6423bd1e 100644 --- a/include/uapi/linux/mdio.h +++ b/include/uapi/linux/mdio.h @@ -116,6 +116,12 @@ #define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT | 0x00) /* 10PASS-TS/2BASE-TL */ #define MDIO_CTRL1_SPEED10P2B (MDIO_CTRL1_SPEEDSELEXT | 0x04) +/* 100 Gb/s */ +#define MDIO_CTRL1_SPEED100G (MDIO_CTRL1_SPEEDSELEXT | 0x0c) +/* 25 Gb/s */ +#define MDIO_CTRL1_SPEED25G (MDIO_CTRL1_SPEEDSELEXT | 0x10) +/* 50 Gb/s */ +#define MDIO_CTRL1_SPEED50G (MDIO_CTRL1_SPEEDSELEXT | 0x14) /* 2.5 Gb/s */ #define MDIO_CTRL1_SPEED2_5G (MDIO_CTRL1_SPEEDSELEXT | 0x18) /* 5 Gb/s */ @@ -137,9 +143,12 @@ #define MDIO_SPEED_10G 0x0001 /* 10G capable */ #define MDIO_PMA_SPEED_2B 0x0002 /* 2BASE-TL capable */ #define MDIO_PMA_SPEED_10P 0x0004 /* 10PASS-TS capable */ +#define MDIO_PMA_SPEED_50G 0x0800 /* 50G capable */ #define MDIO_PMA_SPEED_1000 0x0010 /* 1000M capable */ #define MDIO_PMA_SPEED_100 0x0020 /* 100M capable */ #define MDIO_PMA_SPEED_10 0x0040 /* 10M capable */ +#define MDIO_PMA_SPEED_100G 0x0200 /* 100G capable */ +#define MDIO_PMA_SPEED_25G 0x0800 /* 25G capable */ #define MDIO_PMA_SPEED_2_5G 0x2000 /* 2.5G capable */ #define MDIO_PMA_SPEED_5G 0x4000 /* 5G capable */ #define MDIO_PCS_SPEED_10P2B 0x0002 /* 10PASS-TS/2BASE-TL capable */
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