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Date: Mon, 12 Aug 2013 21:55:22 -0400
From: Daniel Franke <dfoxfranke@...il.com>
To: discussions@...sword-hashing.net
Subject: Re: [PHC] The EARWORM password hash

Samuel Neves <sneves@....uc.pt> writes:

> Since we don't know what area/latency/throughput tradeoffs
> Intel/AMD/future ARM licensees made when implementing AES-NI, it is
> possible that an FPGA/ASIC attacker could have a significant advantage
> over the defender. 

This doesn't worry me.  We already take for granted the defender is
paying for the die area necessary to implement a thousand opcodes that
aren't AESENC.  Whatever shortcuts that Intel took in the implmentation
of the AES circuits are, by comparison, noise.

As I wrote in my reply to CodesInChaos, my security model for EARWORM
assumes that the attacker gets AES circuits for free.  The FPGA/ASIC
attacker's advantage is determined by the extent to which he can improve
on the defender's memory architecture in order to pay less for ROM
bandwidth.

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