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Message-ID: <a5c2f411-ae1a-d98f-0304-b249d190cd6d@ti.com>
Date: Fri, 4 Feb 2022 21:44:18 +0530
From: Kishon Vijay Abraham I <kishon@...com>
To: Jan Kiszka <jan.kiszka@...mens.com>,
Matthias Schiffer <matthias.schiffer@...tq-group.com>,
Nishanth Menon <nm@...com>
CC: Vignesh Raghavendra <vigneshr@...com>,
Tero Kristo <kristo@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/2] arm64: dts: ti: k3-am65: disable optional peripherals
by default
Hi,
On 03/02/22 10:58 pm, Jan Kiszka wrote:
> On 03.02.22 14:06, Matthias Schiffer wrote:
>> On Thu, 2022-02-03 at 12:39 +0100, Jan Kiszka wrote:
>>> On 02.02.22 21:32, Nishanth Menon wrote:
>>>> On 12:25-20220111, Matthias Schiffer wrote:
>>>>> All peripharals that require pinmuxing or other configuration to
>>>>> work
>>>>> should be disabled by default. Dependent DTS are adjusted
>>>>> accordingly.
>>>>>
>>>>> The following nodes are now "disabled" according to dtx_diff and
>>>>> were not
>>>>> overridden to "okay", as they define no pinctrl:
>>>>>
>>>>> k3-am654-base-board:
>>>>> - mcu_i2c0
>>>>> - mcu_spi0..2
>>>>> - cal
>>>>> - main_i2c3
>>>>> - ehrpwm0..5
>>>>> - main_uart1..2
>>>>> - main_spi1..4
>>>>>
>>>>> k3-am65-iot2050*:
>>>>> - mci_spi1..2
>>>>> - cal
>>>>> - ehrpwm0..5
>>>>> - main_spi0..4
>>>>>
>>>>> Signed-off-by: Matthias Schiffer <
>>>>> matthias.schiffer@...tq-group.com>
>>>>
>>>> Jan: you ok with this series? Please ack.
>>>>
>>>
>>> Just rebased the still-too-long backlog to our system fully working
>>> over
>>> mainline.
>>
>> Thanks for testing. As noted earlier, I will send a v2 of this patch
>> that fixes one more inconsistency.
>>
>>> Basically looks good, but this might be a regression of the
>>> patch:
>>>
>>> [ 1.810083] OF: /bus@...000/pcie@...0000: phandle pcie-mode@...0
>>> needs 1, found 0
>>> ...
>>> [ 1.854840] OF: /bus@...000/pcie@...0000: phandle pcie-devid@210
>>> needs 1, found 0
>>>
>>> Jan
>>>
>>
>> That seems to be an older issue, rather than a regression of this
>> patch:
>>
>> k3-am65-main.dtsi defines:
>>
>> ti,syscon-pcie-id = <&pcie_devid>;
>> ti,syscon-pcie-mode = <&pcie0_mode>
>>
>> While according the driver binding docs something like the following is
>> expected:
>>
>> ti,syscon-pcie-id = <&scm_conf 0x0210>;
>> ti,syscon-pcie-mode = <&scm_conf 0x4060>;
>>
>> I assume that the k3-am65-main.dtsi section was imported from ti-linux
>> without accounting for the mainline driver's different binding.
Mainline driver and DT for AM65 used the phandle without the offset. However we
received comments for other platform to convert to use phandle + offset [1]
[1] ->
http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com
This is similar to what is done for other k3 platforms [2]
[2] -> https://lore.kernel.org/all/20210105151421.23237-3-kishon@ti.com/
So as a first step, AM65 driver was modified to support phandle + offset in
commit 7dcf07ac88676a365ce3245b44af2be432f21120.
Update to DT was due and it should be similar to what Jan has posted below
in addition to removing the pcieX_mode and pcie_devid nodes
- pcie0_mode: pcie-mode@...0 {
- compatible = "syscon";
- reg = <0x00004060 0x4>;
- };
-
- pcie1_mode: pcie-mode@...0 {
- compatible = "syscon";
- reg = <0x00004070 0x4>;
- };
-
- pcie_devid: pcie-devid@210 {
- compatible = "syscon";
- reg = <0x00000210 0x4>;
- };
-
Let me know if I have to send a formal patch for this?
Thanks,
Kishon
>>
>
> Yep, 7dcf07ac88676a365ce3245b44af2be432f21120 caused it, and this seems
> to be the fix (though I cannot find a negative impact yet, except for
> the warning):
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> index 09cfdc72c64b..be79c0bc1776 100644
> --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> @@ -694,8 +694,8 @@ pcie0_rc: pcie@...0000 {
> #size-cells = <2>;
> ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>,
> <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
> - ti,syscon-pcie-id = <&pcie_devid>;
> - ti,syscon-pcie-mode = <&pcie0_mode>;
> + ti,syscon-pcie-id = <&scm_conf 0x0210>;
> + ti,syscon-pcie-mode = <&scm_conf 0x4060>;
> bus-range = <0x0 0xff>;
> num-viewport = <16>;
> max-link-speed = <2>;
> @@ -723,7 +723,7 @@ pcie0_ep: pcie-ep@...0000 {
> reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
> reg-names = "app", "dbics", "addr_space", "atu";
> power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
> - ti,syscon-pcie-mode = <&pcie0_mode>;
> + ti,syscon-pcie-mode = <&scm_conf 0x4060>;
> num-ib-windows = <16>;
> num-ob-windows = <16>;
> max-link-speed = <2>;
> @@ -740,8 +740,8 @@ pcie1_rc: pcie@...0000 {
> #size-cells = <2>;
> ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>,
> <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
> - ti,syscon-pcie-id = <&pcie_devid>;
> - ti,syscon-pcie-mode = <&pcie1_mode>;
> + ti,syscon-pcie-id = <&scm_conf 0x0210>;
> + ti,syscon-pcie-mode = <&scm_conf 0x4070>;
> bus-range = <0x0 0xff>;
> num-viewport = <16>;
> max-link-speed = <2>;
> @@ -769,7 +769,7 @@ pcie1_ep: pcie-ep@...0000 {
> reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
> reg-names = "app", "dbics", "addr_space", "atu";
> power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
> - ti,syscon-pcie-mode = <&pcie1_mode>;
> + ti,syscon-pcie-mode = <&scm_conf 0x4070>;
> num-ib-windows = <16>;
> num-ob-windows = <16>;
> max-link-speed = <2>;
>
> Jan
>
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