linux-kernel - Re: [PATCH] x86/speculation: Avoid LFENCE in FILL_RETURN

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Message-ID: <Yv9tj9vbQ9nNlXoY@worktop.programming.kicks-ass.net>
Date:   Fri, 19 Aug 2022 13:01:35 +0200
From:   Peter Zijlstra <peterz@...radead.org>
To:     Ben Hutchings <ben@...adent.org.uk>
Cc:     x86@...nel.org, linux-kernel@...r.kernel.org,
        1017425@...s.debian.org,
        Martin-Éric Racine <martin-eric.racine@....fi>,
        stable@...r.kernel.org, regressions@...ts.linux.dev,
        Daniel Sneddon <daniel.sneddon@...ux.intel.com>,
        Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>
Subject: Re: [PATCH] x86/speculation: Avoid LFENCE in FILL_RETURN_BUFFER on
 CPUs that lack it

On Fri, Aug 19, 2022 at 10:47:21AM +0200, Peter Zijlstra wrote:
> On Fri, Aug 19, 2022 at 02:33:08AM +0200, Ben Hutchings wrote:
> > From: Ben Hutchings <benh@...ian.org>
> > 
> > The mitigation for PBRSB includes adding LFENCE instructions to the
> > RSB filling sequence.  However, RSB filling is done on some older CPUs
> > that don't support the LFENCE instruction.
> > 
> 
> Wait; what? There are chips that enable the RSB mitigations and DONT
> have LFENCE ?!?

So I gave in and clicked on the horrible bugzilla thing. Apparently this
is P3/Athlon64 era crud.

Anyway, the added LFENCE isn't because of retbleed; it is because you
can steer the jnz and terminate the loop early and then not actually
complete the RSB stuffing.

New insights etc.. So it's a geniune fix for the existing rsb stuffing.

I'm not entirly sure what to do here. On the one hand, it's 32bit, so
who gives a crap, otoh we shouldn't break these ancient chips either I
suppose.

How's something like so then? It goes on top of my other patch cleaning
up this RSB mess:

  https://lkml.kernel.org/r/Yv9m%2FhuNJLuyviIn%40worktop.programming.kicks-ass.net

---
Subject: x86/nospec: Fix i386 RSB stuffing

Turns out that i386 doesn't unconditionally have LFENCE, as such the
loop in __FILL_RETURN_BUFFER isn't actually speculation safe on such
chips.

Fixes: ba6e31af2be9 ("x86/speculation: Add LFENCE to RSB fill sequence")
Reported-by: Ben Hutchings <ben@...adent.org.uk>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
---

--- a/arch/x86/include/asm/nospec-branch.h
+++ b/arch/x86/include/asm/nospec-branch.h
@@ -50,6 +50,7 @@
  * the optimal version - two calls, each with their own speculation
  * trap should their return address end up getting used, in a loop.
  */
+#ifdef CONFIG_X86_64
 #define __FILL_RETURN_BUFFER(reg, nr)			\
 	mov	$(nr/2), reg;				\
 771:							\
@@ -60,6 +61,17 @@
 	jnz	771b;					\
 	/* barrier for jnz misprediction */		\
 	lfence;
+#else
+/*
+ * i386 doesn't unconditionally have LFENCE, as such it can't
+ * do a loop.
+ */
+#define __FILL_RETURN_BUFFER(reg, nr)			\
+	.rept nr;					\
+	__FILL_RETURN_SLOT;				\
+	.endr;						\
+	add	$(BITS_PER_LONG/8) * nr, %_ASM_SP;
+#endif
 
 /*
  * Stuff a single RSB slot.