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Date:   Wed, 30 Jun 2021 22:29:03 +0200
From:   Andrew Lunn <andrew@...n.ch>
To:     Robert Hancock <robert.hancock@...ian.com>
Cc:     radhey.shyam.pandey@...inx.com, davem@...emloft.net,
        kuba@...nel.org, linux@...linux.org.uk, netdev@...r.kernel.org
Subject: Re: [PATCH net-next] net: axienet: Allow phytool access to PCS/PMA
 PHY

On Wed, Jun 30, 2021 at 11:40:22AM -0600, Robert Hancock wrote:
> Allow phytool ioctl access to read/write registers in the internal
> PCS/PMA PHY if it is enabled.
> 
> Signed-off-by: Robert Hancock <robert.hancock@...ian.com>
> ---
>  .../net/ethernet/xilinx/xilinx_axienet_main.c | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> index 13cd799541aa..41f2c2255118 100644
> --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> @@ -1213,10 +1213,29 @@ static void axienet_poll_controller(struct net_device *ndev)
>  static int axienet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
>  {
>  	struct axienet_local *lp = netdev_priv(dev);
> +	struct mii_ioctl_data *mii = if_mii(rq);
>  
>  	if (!netif_running(dev))
>  		return -EINVAL;
>  
> +	if (lp->pcs_phy && lp->pcs_phy->addr == mii->phy_id) {
> +		int ret;
> +
> +		switch (cmd) {
> +		case SIOCGMIIREG:
> +			ret = mdiobus_read(lp->pcs_phy->bus, mii->phy_id, mii->reg_num);
> +			if (ret >= 0) {
> +				mii->val_out = ret;
> +				ret = 0;
> +			}
> +			return ret;
> +
> +		case SIOCSMIIREG:
> +			return mdiobus_write(lp->pcs_phy->bus, mii->phy_id,
> +					     mii->reg_num, mii->val_in);
> +		}


I would prefer not to allow write. The kernel should be driving the
hardware, and if user space changes values, the kernel has no idea
about it, and can do the wrong things.

      Andrew

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